riscv/rocket-chip
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coreplex: RocketTileWrapper now HasCrossingHelper

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This commit is contained in:
Henry Cook
2017-10-23 09:39:01 -07:00
committed by Wesley W. Terpstra
parent 9fe35382ea
commit b48ab985d0
8 changed files with 161 additions and 243 deletions
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6
src/main/scala/groundtest/Coreplex.scala
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@ -25,8 +25,10 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
})
)}
tiles.flatMap(_.dcacheOpt).foreach {
sbus.fromSyncTiles(BufferParams.default, TileMasterPortParams().adapt(this) _) :=* _.node
tiles.flatMap(_.dcacheOpt).foreach { dc =>
sbus.fromTile(
adapt = TileMasterPortParams(addBuffers = 1).adapt(this) _,
from = dc.node)
}
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes))