coreplex: RocketTileWrapper now HasCrossingHelper
This commit is contained in:
Henry Cook
committed by
Wesley W. Terpstra
Wesley W. Terpstra
parent
9fe35382ea
commit
b48ab985d0
@ -18,6 +18,7 @@ case class TileMasterPortParams(
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addBuffers: Int = 0,
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blockerCtrlAddr: Option[BigInt] = None,
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cork: Option[Boolean] = None) {
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def adapt(coreplex: HasPeripheryBus)
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(masterNode: TLOutwardNode)
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(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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@ -29,16 +30,15 @@ case class TileMasterPortParams(
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val tile_master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
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val tile_master_buffer = LazyModule(new TLBufferChain(addBuffers))
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tile_master_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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val node: Option[TLNode] = TLNodeChain(List(
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Some(tile_master_buffer.node),
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Some(tile_master_fixer.node),
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tile_master_blocker.map(_.node),
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tile_master_cork.map(_.node)).flatten)
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val node: Option[TLNode] = SourceCardinality { implicit p =>
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TLNodeChain(List(
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Some(tile_master_buffer.node),
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Some(tile_master_fixer.node),
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tile_master_blocker.map(_.node),
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tile_master_cork.map(_.node)).flatten)
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}
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tile_master_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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node.foreach { _ :=* masterNode }
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node.getOrElse(masterNode)
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}
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}
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@ -46,6 +46,7 @@ case class TileMasterPortParams(
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case class TileSlavePortParams(
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addBuffers: Int = 0,
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blockerCtrlAddr: Option[BigInt] = None) {
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def adapt(coreplex: HasPeripheryBus)
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(masterNode: TLOutwardNode)
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(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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@ -55,14 +56,13 @@ case class TileSlavePortParams(
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.map(bp => LazyModule(new BasicBusBlocker(bp)))
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val tile_slave_buffer = LazyModule(new TLBufferChain(addBuffers))
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tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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val node: Option[TLNode] = TLNodeChain(List(
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Some(tile_slave_buffer.node),
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tile_slave_blocker.map(_.node)).flatten)
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val node: Option[TLNode] = SinkCardinality { implicit p =>
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TLNodeChain(List(
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Some(tile_slave_buffer.node),
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tile_slave_blocker.map(_.node)).flatten)
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}
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tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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node.foreach { _ :*= masterNode }
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node.getOrElse(masterNode)
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}
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}
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@ -70,7 +70,8 @@ case class TileSlavePortParams(
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case class RocketCrossingParams(
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crossingType: CoreplexClockCrossing = SynchronousCrossing(),
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master: TileMasterPortParams = TileMasterPortParams(),
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slave: TileSlavePortParams = TileSlavePortParams()) {
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slave: TileSlavePortParams = TileSlavePortParams(),
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boundaryBuffers: Boolean = false) {
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def knownRatio: Option[Int] = crossingType match {
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case RationalCrossing(_) => Some(2)
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case _ => None
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@ -95,67 +96,72 @@ trait HasRocketTiles extends HasTiles
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case NumRocketTiles => crossingParams
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case _ => throw new Exception("RocketCrossingKey.size must == 1 or == RocketTilesKey.size")
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}
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private val crossingTuples = localIntNodes.zip(tileParams).zip(crossings)
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// Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
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// according to the specified type of clock crossing.
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private val crossingTuples = localIntNodes.zip(tileParams).zip(crossings)
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val tiles: Seq[BaseTile] = crossingTuples.map { case ((lip, tp), crossing) =>
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val pWithExtra = p.alterPartial {
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case TileKey => tp
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case BuildRoCC => tp.rocc
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case SharedMemoryTLEdge => sharedMemoryTLEdge
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case RocketCrossingKey => List(crossing)
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}
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// For legacy reasons, it is convenient to store some state
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// in the global Parameters about the specific tile being built now
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val wrapper = LazyModule(new RocketTileWrapper(
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params = tp,
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crossing = crossing.crossingType,
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boundaryBuffers = crossing.boundaryBuffers
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)(p.alterPartial {
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case TileKey => tp
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case BuildRoCC => tp.rocc
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case SharedMemoryTLEdge => sharedMemoryTLEdge
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case RocketCrossingKey => List(crossing)
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})
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).suggestName(tp.name)
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val wrapper = crossing.crossingType match {
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case SynchronousCrossing(params) => {
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val wrapper = LazyModule(new SyncRocketTile(tp)(pWithExtra))
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sbus.fromSyncTiles(params, crossing.master.adapt(this) _, tp.name) :=* wrapper.masterNode
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FlipRendering { implicit p => wrapper.slaveNode:*= pbus.toSyncSlaves(crossing.slave.adapt(this) _, tp.name) }
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wrapper
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}
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case AsynchronousCrossing(depth, sync) => {
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val wrapper = LazyModule(new AsyncRocketTile(tp)(pWithExtra))
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sbus.fromAsyncTiles(depth, sync, crossing.master.adapt(this) _, tp.name) :=* wrapper.masterNode
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FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, crossing.slave.adapt(this) _, tp.name) }
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wrapper
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}
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case RationalCrossing(direction) => {
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val wrapper = LazyModule(new RationalRocketTile(tp)(pWithExtra))
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sbus.fromRationalTiles(direction, crossing.master.adapt(this) _, tp.name) :=* wrapper.masterNode
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FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toRationalSlaves(crossing.slave.adapt(this) _, tp.name) }
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wrapper
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}
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}
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tp.name.foreach(wrapper.suggestName) // Try to stabilize this name for downstream tools
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// Connect the master ports of the tile to the system bus
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sbus.fromTile(
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adapt = {x: TLOutwardNode => wrapper.cross(x) } andThen
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crossing.master.adapt(this) _,
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from = wrapper.masterNode,
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name = tp.name)
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// Local Interrupts must be synchronized to the core clock
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// before being passed into this module.
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// This allows faster latency for interrupts which are already synchronized.
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// The CLINT and PLIC outputs interrupts that are synchronous to the periphery clock,
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// so may or may not need to be synchronized depending on the Tile's crossing type.
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// Debug interrupt is definitely asynchronous in all cases.
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val asyncIntXbar = LazyModule(new IntXbar)
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asyncIntXbar.suggestName("asyncIntXbar")
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asyncIntXbar.intnode := debug.intnode // debug
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wrapper.asyncIntNode := asyncIntXbar.intnode
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// Connect the slave ports of the tile to the periphery bus
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pbus.toTile(
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adapt = {x: TLOutwardNode => wrapper.cross(x) } compose
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crossing.slave.adapt(this) _,
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to = wrapper.slaveNode,
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name = tp.name)
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val periphIntXbar = LazyModule(new IntXbar)
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periphIntXbar.suggestName("periphIntXbar")
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periphIntXbar.intnode := clint.intnode // msip+mtip
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periphIntXbar.intnode := plic.intnode // meip
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// Handle all the different types of interrupts crossing to or from the tile:
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// 1. Debug interrupt is definitely asynchronous in all cases.
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// 2. The CLINT and PLIC output interrupts are synchronous to the periphery clock,
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// so might need to be synchronized depending on the Tile's crossing type.
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// 3. Local Interrupts are required to already be synchronous to the tile clock.
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// 4. Interrupts coming out of the tile are sent to the PLIC,
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// so might need to be synchronized depending on the Tile's crossing type.
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// NOTE: The order of calls to := matters! They must match how interrupts
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// are decoded from rocket.intNode inside the tile.
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val asyncIntXbar = LazyModule(new IntXbar).suggestName(tp.name.map(_ + "AsyncIntXbar"))
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asyncIntXbar.intnode := debug.intnode // debug
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wrapper.intXbar.intnode := wrapper.cross( // 1. always crosses
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name = tp.name.map(_ + "AsyncIntXbar"),
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overrideCrossing = Some(AsynchronousCrossing(8,3))
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)(x = asyncIntXbar.intnode)
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val periphIntXbar = LazyModule(new IntXbar).suggestName(tp.name.map(_ + "PeriphIntXbar"))
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periphIntXbar.intnode := clint.intnode // msip+mtip
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periphIntXbar.intnode := plic.intnode // meip
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if (tp.core.useVM) periphIntXbar.intnode := plic.intnode // seip
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wrapper.periphIntNode := periphIntXbar.intnode
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wrapper.intXbar.intnode := wrapper.cross( // 2. conditionally crosses
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name = tp.name.map(_ + "PeriphIntXbar")
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)(x = periphIntXbar.intnode)
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val coreIntXbar = LazyModule(new IntXbar)
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coreIntXbar.suggestName("coreIntXbar")
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lip.foreach { coreIntXbar.intnode := _ } // lip
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wrapper.coreIntNode := coreIntXbar.intnode
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val coreIntXbar = LazyModule(new IntXbar).suggestName(tp.name.map(_ + "CoreIntXbar"))
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lip.foreach { coreIntXbar.intnode := _ } // lip
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wrapper.intXbar.intnode := coreIntXbar.intnode // 3. never crosses
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wrapper.intOutputNode.foreach { case int =>
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val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency))
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FlipRendering { implicit p => rocketIntXing.intnode := int }
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plic.intnode := rocketIntXing.intnode
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wrapper.rocket.intOutputNode.foreach { i => // 4. conditionally crosses
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plic.intnode := FlipRendering { implicit p =>
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wrapper.cross(name = tp.name.map(_ + "PeriphIntOutput"))(x = i)
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}
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}
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wrapper
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