riscv/rocket-chip
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coreplex: RocketTileWrapper now HasCrossingHelper

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This commit is contained in:
Henry Cook
2017-10-23 09:39:01 -07:00
committed by Wesley W. Terpstra
parent 9fe35382ea
commit b48ab985d0
8 changed files with 161 additions and 243 deletions
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60
src/main/scala/coreplex/CrossingWrapper.scala
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@@ -7,30 +7,34 @@ import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
/** Enumerates the three types of clock crossing between tiles and system bus */
sealed trait CoreplexClockCrossing
case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing
case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing
case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing
trait HasCrossingHelper extends LazyScope
{
this: LazyModule =>
val crossing: CoreplexClockCrossing
def cross(x: TLCrossableNode, name: String): TLOutwardNode = {
def cross(x: TLCrossableNode): TLOutwardNode = {
val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
crossing match {
case SynchronousCrossing(params) => {
val buffer = this { LazyModule(new TLBuffer(params)) }
buffer.suggestName(name + "SynchronousBuffer")
buffer.node := x.node
buffer.node
// !!! Why does star resolution fail for tile with no slave devices?
// this { TLBuffer(params)(x.node) }
x.node
}
case RationalCrossing(direction) => {
def sourceGen = LazyModule(new TLRationalCrossingSource)
def sinkGen = LazyModule(new TLRationalCrossingSink(direction))
val source = if (out) this { sourceGen } else sourceGen
val sink = if (out) sinkGen else this { sinkGen }
source.suggestName(name + "RationalSource")
sink.suggestName(name + "RationalSink")
source.node := x.node
sink.node := source.node
source.node :=? x.node
sink.node :=? source.node
sink.node
}
case AsynchronousCrossing(depth, sync) => {
@@ -38,27 +42,29 @@ trait HasCrossingHelper extends LazyScope
def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
val source = if (out) this { sourceGen } else sourceGen
val sink = if (out) sinkGen else this { sinkGen }
source.suggestName(name + "AsynchronousSource")
sink.suggestName(name + "AsynchronousSink")
source.node := x.node
sink.node := source.node
source.node :=? x.node
sink.node :=? source.node
sink.node
}
}
}
def cross(x: IntCrossableNode, name: String, alreadyRegistered: Boolean = false): IntOutwardNode = {
def cross(
name: Option[String] = None,
alreadyRegistered: Boolean = false,
overrideCrossing: Option[CoreplexClockCrossing] = None)
(x: IntCrossableNode): IntOutwardNode = {
val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
crossing match {
overrideCrossing.getOrElse(crossing) match {
case SynchronousCrossing(_) => {
def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
def sinkGen = LazyModule(new IntSyncCrossingSink(0))
val source = if (out) this { sourceGen } else sourceGen
val sink = if (out) sinkGen else this { sinkGen }
source.suggestName(name + "SyncSource")
sink.suggestName(name + "SyncSink")
source.node := x.node
sink.node := source.node
name.map(_ + "SyncSource").foreach(source.suggestName)
name.map(_ + "SyncSink").foreach(sink.suggestName)
source.node :=? x.node
sink.node :=? source.node
sink.node
}
case RationalCrossing(_) => {
@@ -66,10 +72,10 @@ trait HasCrossingHelper extends LazyScope
def sinkGen = LazyModule(new IntSyncCrossingSink(1))
val source = if (out) this { sourceGen } else sourceGen
val sink = if (out) sinkGen else this { sinkGen }
source.suggestName(name + "SyncSource")
sink.suggestName(name + "SyncSink")
source.node := x.node
sink.node := source.node
name.map(_ + "SyncSource").foreach(source.suggestName)
name.map(_ + "SyncSink").foreach(sink.suggestName)
source.node :=? x.node
sink.node :=? source.node
sink.node
}
case AsynchronousCrossing(_, sync) => {
@@ -77,10 +83,10 @@ trait HasCrossingHelper extends LazyScope
def sinkGen = LazyModule(new IntSyncCrossingSink(sync))
val source = if (out) this { sourceGen } else sourceGen
val sink = if (out) sinkGen else this { sinkGen }
source.suggestName(name + "SyncSource")
sink.suggestName(name + "SyncSink")
source.node := x.node
sink.node := source.node
name.map(_ + "SyncSource").foreach(source.suggestName)
name.map(_ + "SyncSink").foreach(sink.suggestName)
source.node :=? x.node
sink.node :=? source.node
sink.node
}
}