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coreplex: RocketTileWrapper now HasCrossingHelper

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This commit is contained in:
Henry Cook
2017-10-23 09:39:01 -07:00
committed by Wesley W. Terpstra
parent 9fe35382ea
commit b48ab985d0
8 changed files with 161 additions and 243 deletions
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6
src/main/scala/coreplex/BaseCoreplex.scala
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@ -12,12 +12,6 @@ import freechips.rocketchip.tile.{BaseTile, TileParams, SharedMemoryTLEdge, HasE
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.util._
/** Enumerates the three types of clock crossing between tiles and system bus */
sealed trait CoreplexClockCrossing
case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing
case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing
case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing
/** BareCoreplex is the root class for creating a coreplex sub-system */
abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope {
lazy val dts = DTS(bindingTree)