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debug: correctly consider .transfer bit in COMMAND

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Megan Wachs 2017-04-12 21:18:01 -07:00 committed by Yunsup Lee
parent 79477fbea6
commit b44d5f9386
1 changed files with 2 additions and 2 deletions
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src/main/scala/uncore/devices/debug/Debug.scala
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@ -915,8 +915,8 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
val commandRegIsUnsupported = Wire(init = true.B) val commandRegIsUnsupported = Wire(init = true.B)
val commandRegBadHaltResume = Wire(init = false.B) val commandRegBadHaltResume = Wire(init = false.B)
when (commandRegIsAccessRegister && accessRegisterCommandReg.transfer) { when (commandRegIsAccessRegister) {
when ((accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U)){ when (!accessRegisterCommandReg.transfer || (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U)){
commandRegIsUnsupported := false.B commandRegIsUnsupported := false.B
commandRegBadHaltResume := ~hartHalted commandRegBadHaltResume := ~hartHalted
} }