riscv/rocket-chip
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Final parameter refactor

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This commit is contained in:
Henry Cook
2014-09-01 13:28:58 -07:00
parent 2d6aafc32e
commit b42a2ab40a
7 changed files with 93 additions and 96 deletions
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2
rocket/src/main/scala/dpath.scala
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@ -171,7 +171,7 @@ class Datapath extends Module
io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(params(VAddrBits)-1,0)).toUInt
io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
require(io.dmem.req.bits.tag.getWidth >= 6)
require(params(DcacheReqTagBits) >= 6)
require(params(CoreDCacheReqTagBits) >= 6)
// processor control regfile read
val pcr = Module(new CSRFile)