riscv/rocket-chip
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Final parameter refactor

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This commit is contained in:
Henry Cook
2014-09-01 13:28:58 -07:00
parent 2d6aafc32e
commit b42a2ab40a
7 changed files with 93 additions and 96 deletions
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43
rocket/src/main/scala/core.scala
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@ -2,10 +2,34 @@ package rocket
import Chisel._
import Util._
import uncore.HTIFIO
import uncore._
case object FPUParams extends Field[PF]
case object BuildFPU extends Field[Option[() => FPU]]
case object XprLen extends Field[Int]
case object NMultXpr extends Field[Int]
case object RetireWidth extends Field[Int]
case object UseVM extends Field[Boolean]
case object FastLoadWord extends Field[Boolean]
case object FastLoadByte extends Field[Boolean]
case object FastMulDiv extends Field[Boolean]
case object CoreInstBits extends Field[Int]
case object CoreDataBits extends Field[Int]
case object CoreDCacheReqTagBits extends Field[Int]
abstract trait CoreParameters extends UsesParameters {
val xprLen = params(XprLen)
val coreInstBits = params(CoreInstBits)
val coreInstBytes = coreInstBits/8
val coreDataBits = xprLen
val coreDataBytes = coreDataBits/8
val coreDCacheReqTagBits = params(CoreDCacheReqTagBits)
val coreMaxAddrBits = math.max(params(PPNBits),params(VPNBits)+1) + params(PgIdxBits)
if(params(FastLoadByte)) require(params(FastLoadWord))
require(params(RetireWidth) == 1) // for now...
}
abstract class CoreBundle extends Bundle with CoreParameters
abstract class CoreModule extends Module with CoreParameters
class RocketIO extends Bundle
{
@ -16,19 +40,20 @@ class RocketIO extends Bundle
val rocc = new RoCCInterface().flip
}
class Core extends Module
class Core extends Module with CoreParameters
{
val io = new RocketIO
val ctrl = Module(new Control)
val dpath = Module(new Datapath)
if (!params(BuildFPU).isEmpty) {
val p = Some(params.alter(params(FPUParams)))
val fpu = Module(params(BuildFPU).get())(p)
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
}
//If so specified, build an FPU module and wire it in
params(BuildFPU)
.map { bf => Module(bf()) }
.foreach { fpu =>
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
}
ctrl.io.dpath <> dpath.io.ctrl
dpath.io.host <> io.host