riscv/rocket-chip
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Final parameter refactor

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This commit is contained in:
Henry Cook
2014-09-01 13:28:58 -07:00
parent 2d6aafc32e
commit b42a2ab40a
7 changed files with 93 additions and 96 deletions
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4
rocket/src/main/scala/btb.scala
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@ -5,13 +5,13 @@ import Util._
import Node._
import uncore._
case object BTBEntries extends Field[Int]
case object NBTBEntries extends Field[Int]
case object NRAS extends Field[Int]
abstract trait BTBParameters extends UsesParameters {
val vaddrBits = params(VAddrBits)
val matchBits = params(PgIdxBits)
val entries = params(BTBEntries)
val entries = params(NBTBEntries)
val nRAS = params(NRAS)
val nPages = ((1 max(log2Up(entries)))+1)/2*2 // control logic assumes 2 divides pages
val opaqueBits = log2Up(entries)