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Merge pull request #523 from ucb-bar/buffer-move

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coreplex: move TLBuffers for L2 and socBus
This commit is contained in:
Wesley W. Terpstra 2017-01-21 14:53:51 -08:00 committed by GitHub
commit b3ef146805
1 changed files with 4 additions and 5 deletions
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9
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -34,9 +34,8 @@ trait CoreplexNetwork extends HasCoreplexParameters {
l1tol2.node))) l1tol2.node)))
mmio := mmio :=
TLBuffer()(
TLWidthWidget(l1tol2_beatBytes)( TLWidthWidget(l1tol2_beatBytes)(
l1tol2.node)) l1tol2.node)
} }
trait CoreplexNetworkBundle extends HasCoreplexParameters { trait CoreplexNetworkBundle extends HasCoreplexParameters {
@ -78,8 +77,8 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes) val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
for (i <- 0 until l2Config.nBanksPerChannel) { for (i <- 0 until l2Config.nBanksPerChannel) {
val (in, out) = l2Config.coherenceManager(p) val (in, out) = l2Config.coherenceManager(p)
in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node) in := l1tol2.node
bankBar.node := out bankBar.node := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(out)
} }
} }
} }
@ -99,7 +98,7 @@ trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule {
trait HasL2MasterPort extends CoreplexNetwork { trait HasL2MasterPort extends CoreplexNetwork {
val module: HasL2MasterPortModule val module: HasL2MasterPortModule
val l2in = TLInputNode() val l2in = TLInputNode()
l1tol2.node := l2in l1tol2.node := TLBuffer()(l2in)
} }
trait HasL2MasterPortBundle extends CoreplexNetworkBundle { trait HasL2MasterPortBundle extends CoreplexNetworkBundle {