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Merge branch 'l2-subblock-merging' of github.com:ucb-bar/uncore into l2-subblock-merging

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This commit is contained in:
Henry Cook 2015-03-17 22:46:54 -07:00
commit b364d387de
1 changed files with 11 additions and 11 deletions
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22
uncore/src/main/scala/cache.scala
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@ -172,7 +172,6 @@ abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgen
require(amoAluOperandBits <= innerDataBits) require(amoAluOperandBits <= innerDataBits)
require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states
val nSecondaryMisses = 4 val nSecondaryMisses = 4
val enableGetMerging = false
} }
abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
@ -708,8 +707,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
val mergeDataInner = mergeData(innerDataBits) _ val mergeDataInner = mergeData(innerDataBits) _
val mergeDataOuter = mergeData(outerDataBits) _ val mergeDataOuter = mergeData(outerDataBits) _
val can_merge_iacq_get = Bool(enableGetMerging) && val can_merge_iacq_get = (xact.isBuiltInType(Acquire.getType) &&
(xact.isBuiltInType(Acquire.getType) &&
io.iacq().isBuiltInType(Acquire.getType)) && io.iacq().isBuiltInType(Acquire.getType)) &&
(xact_src === io.inner.acquire.bits.header.src) && (xact_src === io.inner.acquire.bits.header.src) &&
xact.conflicts(io.iacq()) && xact.conflicts(io.iacq()) &&
@ -825,7 +823,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
xact.data := UInt(0) xact.data := UInt(0)
wmask_buffer.foreach { w => w := UInt(0) } wmask_buffer.foreach { w => w := UInt(0) }
pending_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType), pending_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
UInt(0), addPendingBitWhenHasData(io.inner.acquire),
SInt(-1, width = innerDataBeats)).toUInt SInt(-1, width = innerDataBeats)).toUInt
pending_reads := Mux(io.iacq().isSubBlockType(), pending_reads := Mux(io.iacq().isSubBlockType(),
addPendingBitWhenWmaskIsNotFull(io.inner.acquire), addPendingBitWhenWmaskIsNotFull(io.inner.acquire),
@ -993,13 +991,15 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
} }
// Handle Get and Put merging // Handle Get and Put merging
when(io.inner.acquire.fire() && io.iacq().hasData()) { when(io.inner.acquire.fire()) {
val beat = io.iacq().addr_beat when (io.iacq().hasData()) {
val wmask = io.iacq().wmask() val beat = io.iacq().addr_beat
val full = FillInterleaved(8, wmask) val wmask = io.iacq().wmask()
data_buffer(beat) := (~full & data_buffer(beat)) | (full & io.iacq().data) val full = FillInterleaved(8, wmask)
wmask_buffer(beat) := wmask | Mux(state === s_idle, Bits(0), wmask_buffer(beat)) data_buffer(beat) := (~full & data_buffer(beat)) | (full & io.iacq().data)
when(!xact.hasMultibeatData()) { ignt_q.io.enq.valid := Bool(true) } wmask_buffer(beat) := wmask | Mux(state === s_idle, Bits(0), wmask_buffer(beat))
}
when(!io.iacq().hasMultibeatData()) { ignt_q.io.enq.valid := Bool(true) }
} }
assert(!(state != s_idle && io.inner.acquire.fire() && assert(!(state != s_idle && io.inner.acquire.fire() &&