riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink: TestSRAM reports errors on illegal access

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-07-07 21:13:07 -07:00
parent e8cb6dafd3
commit b2cc4b99ed
1 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/devices/tilelink/TestRAM.scala
View File

@@ -49,12 +49,13 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
in.d.valid := in.a.valid in.d.valid := in.a.valid
val hasData = edge.hasData(in.a.bits) val hasData = edge.hasData(in.a.bits)
val legal = address.contains(in.a.bits.address)
val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) } val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) }
in.d.bits := edge.AccessAck(in.a.bits, UInt(0)) in.d.bits := edge.AccessAck(in.a.bits, UInt(0), !legal)
in.d.bits.data := Cat(mem(memAddress).reverse) in.d.bits.data := Cat(mem(memAddress).reverse)
in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData) in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
when (in.a.fire() && hasData) { mem.write(memAddress, wdata, in.a.bits.mask.toBools) } when (in.a.fire() && hasData && legal) { mem.write(memAddress, wdata, in.a.bits.mask.toBools) }
// Tie off unused channels // Tie off unused channels
in.b.valid := Bool(false) in.b.valid := Bool(false)