diff --git a/src/main/scala/devices/tilelink/TestRAM.scala b/src/main/scala/devices/tilelink/TestRAM.scala
index 38a18260..d6d27edb 100644
--- a/src/main/scala/devices/tilelink/TestRAM.scala
+++ b/src/main/scala/devices/tilelink/TestRAM.scala
@@ -49,12 +49,13 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
     in.d.valid := in.a.valid
 
     val hasData = edge.hasData(in.a.bits)
+    val legal = address.contains(in.a.bits.address)
     val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) }
 
-    in.d.bits := edge.AccessAck(in.a.bits, UInt(0))
+    in.d.bits := edge.AccessAck(in.a.bits, UInt(0), !legal)
     in.d.bits.data := Cat(mem(memAddress).reverse)
     in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
-    when (in.a.fire() && hasData) { mem.write(memAddress, wdata, in.a.bits.mask.toBools) }
+    when (in.a.fire() && hasData && legal) { mem.write(memAddress, wdata, in.a.bits.mask.toBools) }
 
     // Tie off unused channels
     in.b.valid := Bool(false)