riscv/rocket-chip
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Conditionalize some covers that are sometimes impossible (#1043)

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This commit is contained in:
Andrew Waterman 2017-10-10 17:14:33 -07:00 committed by GitHub
parent ef28ce8d2f
commit b2bc46471b
2 changed files with 6 additions and 3 deletions
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3
src/main/scala/rocket/DCache.scala
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@ -393,7 +393,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val a_size = mtSize(s2_req.typ)
val a_data = Fill(beatWords, pstore1_data)
val acquire = if (edge.manager.anySupportAcquireB) {
ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked")
edge.AcquireBlock(UInt(0), acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb
} else {
Wire(new TLBundleA(edge.bundle))
@ -655,6 +654,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
io.cpu.s2_xcpt := 0.U.asTypeOf(io.cpu.s2_xcpt)
}
assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC)))
} else {
ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked")
}
// uncached response

4
src/main/scala/rocket/PTW.scala
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@ -279,8 +279,10 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
count := pgLevels-1
}
if (usingVM) {
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(io.mem.resp.valid && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, s"PTW_$label", "MemorySystem;;" + desc)