From b2bc46471b08570d2562c86e9cef6cfaa8d694f4 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <aswaterman@gmail.com>
Date: Tue, 10 Oct 2017 17:14:33 -0700
Subject: [PATCH] Conditionalize some covers that are sometimes impossible
 (#1043)

---
 src/main/scala/rocket/DCache.scala | 3 ++-
 src/main/scala/rocket/PTW.scala    | 6 ++++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
index ed185b93..feeaf508 100644
--- a/src/main/scala/rocket/DCache.scala
+++ b/src/main/scala/rocket/DCache.scala
@@ -393,7 +393,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val a_size = mtSize(s2_req.typ)
   val a_data = Fill(beatWords, pstore1_data)
   val acquire = if (edge.manager.anySupportAcquireB) {
-    ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked")
     edge.AcquireBlock(UInt(0), acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb
   } else {
     Wire(new TLBundleA(edge.bundle))
@@ -655,6 +654,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
       io.cpu.s2_xcpt := 0.U.asTypeOf(io.cpu.s2_xcpt)
     }
     assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC)))
+  } else {
+    ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked")
   }
 
   // uncached response
diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala
index 125c33ba..43fe7497 100644
--- a/src/main/scala/rocket/PTW.scala
+++ b/src/main/scala/rocket/PTW.scala
@@ -279,8 +279,10 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
     count := pgLevels-1
   }
 
-  ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
-  ccover(io.mem.resp.valid && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
+  if (usingVM) {
+    ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
+    ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
+  }
 
   def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
     cover(cond, s"PTW_$label", "MemorySystem;;" + desc)