riscv/rocket-chip
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Conditionalize some covers that are sometimes impossible (#1043)

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This commit is contained in:
Andrew Waterman
2017-10-10 17:14:33 -07:00
committed by GitHub
parent ef28ce8d2f
commit b2bc46471b
2 changed files with 6 additions and 3 deletions
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6
src/main/scala/rocket/PTW.scala
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@ -279,8 +279,10 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
count := pgLevels-1
}
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(io.mem.resp.valid && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
if (usingVM) {
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, s"PTW_$label", "MemorySystem;;" + desc)