riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Fix zero-width wire issues when ITIM is disabled

Browse Source
This commit is contained in:
Andrew Waterman 2017-04-26 22:43:00 -07:00
parent e23ee274f6
commit b2b4725522
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/rocket/ICache.scala
View File

@ -88,14 +88,14 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
require(!usingVM || pgIdxBits >= untagBits) require(!usingVM || pgIdxBits >= untagBits)
val scratchpadOn = RegInit(false.B) val scratchpadOn = RegInit(false.B)
val scratchpadMax = Reg(UInt(width = log2Ceil(nSets * (nWays - 1)))) val scratchpadMax = tl_in.map(tl => Reg(UInt(width = log2Ceil(nSets * (nWays - 1)))))
def lineInScratchpad(line: UInt) = scratchpadOn && line <= scratchpadMax def lineInScratchpad(line: UInt) = scratchpadMax.map(scratchpadOn && line <= _).getOrElse(false.B)
def addrMaybeInScratchpad(addr: UInt) = if (outer.icacheParams.itimAddr.isEmpty) false.B else { def addrMaybeInScratchpad(addr: UInt) = if (outer.icacheParams.itimAddr.isEmpty) false.B else {
val base = GetPropertyByHartId(p(coreplex.RocketTilesKey), _.icache.flatMap(_.itimAddr.map(_.U)), io.hartid) val base = GetPropertyByHartId(p(coreplex.RocketTilesKey), _.icache.flatMap(_.itimAddr.map(_.U)), io.hartid)
addr >= base && addr < base + outer.size addr >= base && addr < base + outer.size
} }
def addrInScratchpad(addr: UInt) = addrMaybeInScratchpad(addr) && lineInScratchpad(addr(untagBits+log2Ceil(nWays)-1, blockOffBits)) def addrInScratchpad(addr: UInt) = addrMaybeInScratchpad(addr) && lineInScratchpad(addr(untagBits+log2Ceil(nWays)-1, blockOffBits))
def scratchpadWay(addr: UInt) = addr(untagBits+log2Ceil(nWays)-1, untagBits) def scratchpadWay(addr: UInt) = addr.extract(untagBits+log2Ceil(nWays)-1, untagBits)
def scratchpadWayValid(way: UInt) = way < nWays - 1 def scratchpadWayValid(way: UInt) = way < nWays - 1
def scratchpadLine(addr: UInt) = addr(untagBits+log2Ceil(nWays)-1, blockOffBits) def scratchpadLine(addr: UInt) = addr(untagBits+log2Ceil(nWays)-1, blockOffBits)
val s0_slaveValid = tl_in.map(_.a.fire()).getOrElse(false.B) val s0_slaveValid = tl_in.map(_.a.fire()).getOrElse(false.B)
@ -170,7 +170,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
for (i <- 0 until nWays) { for (i <- 0 until nWays) {
val s1_idx = io.s1_paddr(untagBits-1,blockOffBits) val s1_idx = io.s1_paddr(untagBits-1,blockOffBits)
val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits) val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits)
val scratchpadHit = Bool(i < nWays-1) && val scratchpadHit = scratchpadWayValid(i) &&
Mux(s1_slaveValid, Mux(s1_slaveValid,
lineInScratchpad(scratchpadLine(s1s3_slaveAddr)) && scratchpadWay(s1s3_slaveAddr) === i, lineInScratchpad(scratchpadLine(s1s3_slaveAddr)) && scratchpadWay(s1s3_slaveAddr) === i,
addrInScratchpad(io.s1_paddr) && scratchpadWay(io.s1_paddr) === i) addrInScratchpad(io.s1_paddr) && scratchpadWay(io.s1_paddr) === i)
@ -235,7 +235,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
when (edge_in.get.hasData(a)) { when (edge_in.get.hasData(a)) {
val enable = scratchpadWayValid(scratchpadWay(a.address)) val enable = scratchpadWayValid(scratchpadWay(a.address))
when (!lineInScratchpad(scratchpadLine(a.address))) { when (!lineInScratchpad(scratchpadLine(a.address))) {
scratchpadMax := scratchpadLine(a.address) scratchpadMax.get := scratchpadLine(a.address)
when (enable) { invalidate := true } when (enable) { invalidate := true }
} }
scratchpadOn := enable scratchpadOn := enable