riscv/rocket-chip
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rocketchip: move memory channel Xbar from coreplex to rocketchip

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We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
This commit is contained in:
Wesley W. Terpstra
2017-02-03 16:55:44 -08:00
parent fc9ea62d38
commit b240505a15
5 changed files with 27 additions and 30 deletions
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28
src/main/scala/rocketchip/Periphery.scala
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@ -72,28 +72,21 @@ trait PeripheryExtInterruptsModule {
/////
trait PeripheryNoMem extends TopNetwork {
private val channels = p(BankedL2Config).nMemoryChannels
require (channels == 0)
val mem = Seq()
}
/////
trait PeripheryMasterAXI4Mem {
this: TopNetwork =>
val module: PeripheryMasterAXI4MemModule
private val config = p(ExtMem)
private val channels = p(BankedL2Config).nMemoryChannels
private val lineBytes = p(CacheBlockBytes)
val mem_axi4 = AXI4BlindOutputNode(Seq.tabulate(channels) { i =>
val c_size = config.size/channels
val c_base = config.base + c_size*i
val mem_axi4 = AXI4BlindOutputNode(Seq.tabulate(channels) { channel =>
val base = AddressSet(config.base, config.size-1)
val filter = AddressSet(channel * lineBytes, ~((channels-1) * lineBytes))
AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(c_base, c_size-1)),
address = base.intersect(filter).toList,
regionType = RegionType.UNCACHED, // cacheable
executable = true,
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
@ -102,10 +95,13 @@ trait PeripheryMasterAXI4Mem {
beatBytes = config.beatBytes)
})
val mem = Seq.fill(channels) {
val converter = LazyModule(new TLToAXI4(config.idBits))
mem_axi4 := AXI4Buffer()(converter.node)
converter.node
private val converter = LazyModule(new TLToAXI4(config.idBits))
private val buffer = LazyModule(new AXI4Buffer)
mem foreach { case xbar =>
converter.node := xbar.node
buffer.node := converter.node
mem_axi4 := buffer.node
}
}