From b240505a1526eea51811fc985aa369a580333b7a Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 3 Feb 2017 16:55:44 -0800 Subject: [PATCH] rocketchip: move memory channel Xbar from coreplex to rocketchip We want to keep the banks split in the outer SoC if there is an L3. Furthermore, each channel might go to different memory subsystems, like DDR/HMC/Zero, from rocketchip. --- src/main/scala/coreplex/CoreplexNetwork.scala | 21 +++++++------- src/main/scala/groundtest/Top.scala | 2 +- src/main/scala/rocketchip/BaseTop.scala | 1 + src/main/scala/rocketchip/Periphery.scala | 28 ++++++++----------- .../scala/rocketchip/RocketPlexMaster.scala | 5 ++-- 5 files changed, 27 insertions(+), 30 deletions(-) diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala index 9402548b..8d12ee95 100644 --- a/src/main/scala/coreplex/CoreplexNetwork.scala +++ b/src/main/scala/coreplex/CoreplexNetwork.scala @@ -71,27 +71,26 @@ trait CoreplexNetworkModule extends HasCoreplexParameters { trait BankedL2CoherenceManagers extends CoreplexNetwork { val module: BankedL2CoherenceManagersModule + require (isPow2(l2Config.nMemoryChannels)) require (isPow2(l2Config.nBanksPerChannel)) require (isPow2(l1tol2_lineBytes)) - val mem = TLOutputNode() - for (channel <- 0 until l2Config.nMemoryChannels) { - val bankBar = LazyModule(new TLXbar) - val (in, out) = l2Config.coherenceManager(p, this) - - in :*= l1tol2.node - mem := bankBar.node - - val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes) + private val (in, out) = l2Config.coherenceManager(p, this) + private val mask = ~BigInt((l2Config.nBanks-1) * l1tol2_lineBytes) + val mem = Seq.tabulate(l2Config.nMemoryChannels) { channel => + val node = TLOutputNode() for (bank <- 0 until l2Config.nBanksPerChannel) { - bankBar.node := TLFilter(AddressSet(bank * l1tol2_lineBytes, mask))(out) + val offset = (bank * l2Config.nMemoryChannels) + channel + in := l1tol2.node + node := TLFilter(AddressSet(offset * l1tol2_lineBytes, mask))(out) } + node } } trait BankedL2CoherenceManagersBundle extends CoreplexNetworkBundle { val outer: BankedL2CoherenceManagers - val mem = outer.mem.bundleOut + val mem = HeterogeneousBag(outer.mem.map(_.bundleOut)) } trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule { diff --git a/src/main/scala/groundtest/Top.scala b/src/main/scala/groundtest/Top.scala index 5e328089..9fb40686 100644 --- a/src/main/scala/groundtest/Top.scala +++ b/src/main/scala/groundtest/Top.scala @@ -17,7 +17,7 @@ class GroundTestTop(implicit p: Parameters) extends BaseTop socBus.node := coreplex.mmio coreplex.mmioInt := intBus.intnode - mem.foreach { _ := coreplex.mem } + (mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel } } class GroundTestTopBundle[+L <: GroundTestTop](_outer: L) extends BaseTopBundle(_outer) diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index 0a9bdec7..b5a8c582 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -35,6 +35,7 @@ trait TopNetwork extends HasPeripheryParameters { val peripheryBus = LazyModule(new TLXbar) val intBus = LazyModule(new IntXbar) val l2 = LazyModule(new TLBuffer) + val mem = Seq.fill(p(coreplex.BankedL2Config).nMemoryChannels) { LazyModule(new TLXbar) } peripheryBus.node := TLBuffer()( diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index 5e544754..1d05843f 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -72,28 +72,21 @@ trait PeripheryExtInterruptsModule { ///// -trait PeripheryNoMem extends TopNetwork { - private val channels = p(BankedL2Config).nMemoryChannels - require (channels == 0) - val mem = Seq() -} - -///// - trait PeripheryMasterAXI4Mem { this: TopNetwork => val module: PeripheryMasterAXI4MemModule private val config = p(ExtMem) private val channels = p(BankedL2Config).nMemoryChannels + private val lineBytes = p(CacheBlockBytes) - val mem_axi4 = AXI4BlindOutputNode(Seq.tabulate(channels) { i => - val c_size = config.size/channels - val c_base = config.base + c_size*i + val mem_axi4 = AXI4BlindOutputNode(Seq.tabulate(channels) { channel => + val base = AddressSet(config.base, config.size-1) + val filter = AddressSet(channel * lineBytes, ~((channels-1) * lineBytes)) AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( - address = List(AddressSet(c_base, c_size-1)), + address = base.intersect(filter).toList, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers @@ -102,10 +95,13 @@ trait PeripheryMasterAXI4Mem { beatBytes = config.beatBytes) }) - val mem = Seq.fill(channels) { - val converter = LazyModule(new TLToAXI4(config.idBits)) - mem_axi4 := AXI4Buffer()(converter.node) - converter.node + private val converter = LazyModule(new TLToAXI4(config.idBits)) + private val buffer = LazyModule(new AXI4Buffer) + + mem foreach { case xbar => + converter.node := xbar.node + buffer.node := converter.node + mem_axi4 := buffer.node } } diff --git a/src/main/scala/rocketchip/RocketPlexMaster.scala b/src/main/scala/rocketchip/RocketPlexMaster.scala index 0f7d1c05..06591dbb 100644 --- a/src/main/scala/rocketchip/RocketPlexMaster.scala +++ b/src/main/scala/rocketchip/RocketPlexMaster.scala @@ -12,14 +12,15 @@ import coreplex._ trait RocketPlexMaster extends TopNetwork { val module: RocketPlexMasterModule - val mem: Seq[TLInwardNode] val coreplex = LazyModule(new DefaultCoreplex) coreplex.l2in :=* l2.node socBus.node := coreplex.mmio coreplex.mmioInt := intBus.intnode - mem.foreach { _ := coreplex.mem } + + require (mem.size == coreplex.mem.size) + (mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel } } trait RocketPlexMasterBundle extends TopNetworkBundle {