riscv/rocket-chip
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make sure data checked is same as data sent

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This commit is contained in:
Howard Mao 2015-10-26 21:55:04 -07:00
parent 2b252bc6ff
commit b22088d934
1 changed files with 6 additions and 3 deletions
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9
groundtest/src/main/scala/generator.scala
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@ -65,8 +65,11 @@ class UncachedTileLinkGenerator(id: Int, rnd: Random)
io.finished := (state === s_finished) io.finished := (state === s_finished)
val full_addr = Cat(addr_block, acq_beat, UInt(0, tlByteAddrBits)) val acq_addr = Cat(addr_block, acq_beat, UInt(0, tlByteAddrBits))
val put_data = Cat(UInt(id, log2Up(nGens)), req_cnt, full_addr) val gnt_addr = Cat(addr_block, gnt_beat, UInt(0, tlByteAddrBits))
val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt)
val put_data = Cat(data_prefix, acq_addr)
val get_data = Cat(data_prefix, gnt_addr)
val put_acquire = PutBlock( val put_acquire = PutBlock(
client_xact_id = UInt(0), client_xact_id = UInt(0),
@ -83,7 +86,7 @@ class UncachedTileLinkGenerator(id: Int, rnd: Random)
io.tl.grant.ready := !sending io.tl.grant.ready := !sending
assert(!io.tl.grant.valid || state != s_get || assert(!io.tl.grant.valid || state != s_get ||
io.tl.grant.bits.data === put_data, io.tl.grant.bits.data === get_data,
"Get received incorrect data") "Get received incorrect data")
io.tl.release.valid := Bool(false) io.tl.release.valid := Bool(false)