riscv/rocket-chip
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Fix PLIC enable bit access for #ints >= tlDataBits

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This commit is contained in:
Andrew Waterman 2016-10-06 16:21:14 -07:00
parent c22438b822
commit b1c777c7a2
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/uncore/devices/Plic.scala
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@ -140,9 +140,9 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
else UInt(0) else UInt(0)
hart := enableHart hart := enableHart
val word = val word =
if (tlDataBits >= cfg.nHarts) UInt(0) if (tlDataBits >= myEnables.size) UInt(0)
else addr(log2Up((cfg.nHarts+7)/8)-1,log2Up(tlDataBytes)) else addr(log2Ceil((myEnables.size-1)/tlDataBits+1)-1,log2Up(tlDataBytes))
for (i <- 0 until cfg.nHarts by tlDataBits) { for (i <- 0 until myEnables.size by tlDataBits) {
when (word === i/tlDataBits) { when (word === i/tlDataBits) {
rdata := Cat(myEnables.slice(i, i + tlDataBits).reverse) rdata := Cat(myEnables.slice(i, i + tlDataBits).reverse)
for (j <- 0 until (tlDataBits min (myEnables.size - i))) { for (j <- 0 until (tlDataBits min (myEnables.size - i))) {