From b1c777c7a2af75854d36012c7cd2e38f90d6f6da Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 6 Oct 2016 16:21:14 -0700 Subject: [PATCH] Fix PLIC enable bit access for #ints >= tlDataBits --- src/main/scala/uncore/devices/Plic.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala index 4eefb8c7..179737ad 100644 --- a/src/main/scala/uncore/devices/Plic.scala +++ b/src/main/scala/uncore/devices/Plic.scala @@ -140,9 +140,9 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module else UInt(0) hart := enableHart val word = - if (tlDataBits >= cfg.nHarts) UInt(0) - else addr(log2Up((cfg.nHarts+7)/8)-1,log2Up(tlDataBytes)) - for (i <- 0 until cfg.nHarts by tlDataBits) { + if (tlDataBits >= myEnables.size) UInt(0) + else addr(log2Ceil((myEnables.size-1)/tlDataBits+1)-1,log2Up(tlDataBytes)) + for (i <- 0 until myEnables.size by tlDataBits) { when (word === i/tlDataBits) { rdata := Cat(myEnables.slice(i, i + tlDataBits).reverse) for (j <- 0 until (tlDataBits min (myEnables.size - i))) {