riscv/rocket-chip
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add vector irq handler

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This commit is contained in:
Yunsup Lee
2012-03-14 14:15:28 -07:00
parent 040d62f372
commit b19d783fbd
7 changed files with 38 additions and 2 deletions
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8
rocket/src/main/scala/dpath_util.scala
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@ -70,6 +70,8 @@ class ioDpathPCR extends Bundle()
val exception = Bool(INPUT);
val cause = UFix(5, INPUT);
val badvaddr_wen = Bool(INPUT);
val vec_irq_aux = Bits(64, INPUT)
val vec_irq_aux_wen = Bool(INPUT)
val pc = UFix(VADDR_BITS+1, INPUT);
val eret = Bool(INPUT);
val ei = Bool(INPUT);
@ -100,6 +102,7 @@ class rocketDpathPCR extends Component
val reg_k1 = Reg() { Bits() };
val reg_ptbr = Reg() { UFix() };
val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
val reg_vec_irq_aux = Reg() { Bits() }
val reg_error_mode = Reg(resetVal = Bool(false));
val reg_status_vm = Reg(resetVal = Bool(false));
@ -145,6 +148,9 @@ class rocketDpathPCR extends Component
when (io.badvaddr_wen) {
reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
}
when (io.vec_irq_aux_wen) {
reg_vec_irq_aux := io.vec_irq_aux
}
when (io.exception) {
when (!reg_status_et) {
@ -207,6 +213,7 @@ class rocketDpathPCR extends Component
when (waddr === PCR_K1) { reg_k1 := wdata; }
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) }
when (waddr === PCR_VECIRQAUX) { reg_vec_irq_aux := wdata }
}
rdata := Bits(0, 64)
@ -227,6 +234,7 @@ class rocketDpathPCR extends Component
is (PCR_PTBR) { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) }
is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) }
is (PCR_VECIRQAUX){ rdata := reg_vec_irq_aux }
}
}
}