riscv/rocket-chip
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Fixing requirements for PAddrBits (#961)

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Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues.
This commit is contained in:
Shreesha Srinath 2017-08-17 11:53:59 -07:00 committed by Andrew Waterman
parent 1db4b3be9a
commit b1719cfee0
1 changed files with 2 additions and 2 deletions
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src/main/scala/tile/RocketTile.scala
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@ -133,8 +133,8 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
with HasLazyRoCCModule with HasLazyRoCCModule
with CanHaveScratchpadModule { with CanHaveScratchpadModule {
require(outer.p(PAddrBits) >= outer.masterNode.edgesIn(0).bundle.addressBits, require(outer.p(PAddrBits) == outer.masterNode.edgesIn(0).bundle.addressBits,
s"outer.p(PAddrBits) (${outer.p(PAddrBits)}) must be >= outer.masterNode.addressBits (${outer.masterNode.edgesIn(0).bundle.addressBits})") s"outer.p(PAddrBits) (${outer.p(PAddrBits)}) must be == outer.masterNode.addressBits (${outer.masterNode.edgesIn(0).bundle.addressBits})")
val core = Module(p(BuildCore)(outer.p)) val core = Module(p(BuildCore)(outer.p))
decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector