From b1719cfee064e3a7aa124c981ecb1d01e2c2cc3f Mon Sep 17 00:00:00 2001 From: Shreesha Srinath Date: Thu, 17 Aug 2017 11:53:59 -0700 Subject: [PATCH] Fixing requirements for PAddrBits (#961) Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues. --- src/main/scala/tile/RocketTile.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 60b50738..3490b6c9 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -133,8 +133,8 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne with HasLazyRoCCModule with CanHaveScratchpadModule { - require(outer.p(PAddrBits) >= outer.masterNode.edgesIn(0).bundle.addressBits, - s"outer.p(PAddrBits) (${outer.p(PAddrBits)}) must be >= outer.masterNode.addressBits (${outer.masterNode.edgesIn(0).bundle.addressBits})") + require(outer.p(PAddrBits) == outer.masterNode.edgesIn(0).bundle.addressBits, + s"outer.p(PAddrBits) (${outer.p(PAddrBits)}) must be == outer.masterNode.addressBits (${outer.masterNode.edgesIn(0).bundle.addressBits})") val core = Module(p(BuildCore)(outer.p)) decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector