riscv/rocket-chip
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tile: cake reduction

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* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
This commit is contained in:
Henry Cook
2018-01-02 16:03:05 -08:00
parent efe7165b54
commit b0e1bc3071
5 changed files with 56 additions and 68 deletions
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56
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -6,13 +6,12 @@ import Chisel._
import Chisel.ImplicitConversions._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
/* This adapter converts between diplomatic TileLink and non-diplomatic HellaCacheIO */
class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
val node = TLManagerNode(Seq(TLManagerPortParameters(
@ -93,56 +92,3 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics:
tl_in.e.ready := Bool(true)
}
}
/** Mix-ins for constructing tiles that have optional scratchpads */
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend { this: BaseTile =>
val module: CanHaveScratchpadModule
val intOutwardNode = IntIdentityNode()
val slaveNode = TLIdentityNode()
val masterNode = TLIdentityNode()
val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)))
}
scratch.foreach(lm => connectTLSlave(lm.node, xBytes))
val busErrorUnit = tileParams.core.tileControlAddr map { a =>
val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
intOutwardNode := beu.intNode
connectTLSlave(beu.node, xBytes)
beu
}
val tile_master_blocker =
tileParams.blockerCtrlAddr
.map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
.map(bp => LazyModule(new BasicBusBlocker(bp)))
tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes))
// TODO: this doesn't block other masters, e.g. RoCCs
tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node }
masterNode :=* tlOtherMastersNode
tlSlaveXbar.node :*= slaveNode
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node)
require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
finalNode.get.address(0)
}
nDCachePorts += (scratch.isDefined).toInt
}
trait CanHaveScratchpadModule extends HasHellaCacheModule with HasICacheFrontendModule {
val outer: CanHaveScratchpad
outer.scratch.foreach { lm => dcachePorts += lm.module.io.dmem }
outer.busErrorUnit.foreach { lm =>
lm.module.io.errors.dcache := outer.dcache.module.io.errors
lm.module.io.errors.icache := outer.frontend.module.io.errors
}
}