diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index e78fd22d..5989c6bc 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -6,13 +6,12 @@ import Chisel._ import Chisel.ImplicitConversions._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ +/* This adapter converts between diplomatic TileLink and non-diplomatic HellaCacheIO */ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("dtim", Seq("sifive,dtim0")) val node = TLManagerNode(Seq(TLManagerPortParameters( @@ -93,56 +92,3 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics: tl_in.e.ready := Bool(true) } } - -/** Mix-ins for constructing tiles that have optional scratchpads */ -trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend { this: BaseTile => - val module: CanHaveScratchpadModule - - val intOutwardNode = IntIdentityNode() - val slaveNode = TLIdentityNode() - val masterNode = TLIdentityNode() - - val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s => - LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO))) - } - scratch.foreach(lm => connectTLSlave(lm.node, xBytes)) - - val busErrorUnit = tileParams.core.tileControlAddr map { a => - val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a))) - intOutwardNode := beu.intNode - connectTLSlave(beu.node, xBytes) - beu - } - - val tile_master_blocker = - tileParams.blockerCtrlAddr - .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) - .map(bp => LazyModule(new BasicBusBlocker(bp))) - - tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) - - // TODO: this doesn't block other masters, e.g. RoCCs - tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } - masterNode :=* tlOtherMastersNode - tlSlaveXbar.node :*= slaveNode - - - def findScratchpadFromICache: Option[AddressSet] = scratch.map { s => - val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node) - require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?") - require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!") - finalNode.get.address(0) - } - - nDCachePorts += (scratch.isDefined).toInt -} - -trait CanHaveScratchpadModule extends HasHellaCacheModule with HasICacheFrontendModule { - val outer: CanHaveScratchpad - - outer.scratch.foreach { lm => dcachePorts += lm.module.io.dmem } - outer.busErrorUnit.foreach { lm => - lm.module.io.errors.dcache := outer.dcache.module.io.errors - lm.module.io.errors.icache := outer.frontend.module.io.errors - } -} diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 420370ac..088b6134 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -181,6 +181,8 @@ class BaseTileModule[+L <: BaseTile](val outer: L) extends LazyModuleImp(outer) val trace = tileParams.trace.option(IO(Vec(tileParams.core.retireWidth, new TracedInstruction).asOutput)) val constants = IO(new TileInputConstants) + + val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) } /** Some other non-tilelink but still standard inputs */ diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala index 1b88f7ae..77f8c509 100644 --- a/src/main/scala/tile/FPU.scala +++ b/src/main/scala/tile/FPU.scala @@ -874,9 +874,3 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { req } } - -/** Mix-in for constructing tiles that may have an FPU external to the core pipeline */ -trait CanHaveSharedFPUModule[+L <: BaseTile] { this: BaseTileModule[L] => - val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) - // TODO fpArb could go here instead of inside LegacyRoccComplex -} diff --git a/src/main/scala/tile/LazyRoCC.scala b/src/main/scala/tile/LazyRoCC.scala index 2a3d5a7e..9a80bddd 100644 --- a/src/main/scala/tile/LazyRoCC.scala +++ b/src/main/scala/tile/LazyRoCC.scala @@ -90,8 +90,7 @@ trait HasLazyRoCC extends CanHavePTW { this: BaseTile => nDCachePorts += roccs.size } -trait HasLazyRoCCModule[+L <: BaseTile with HasLazyRoCC] extends CanHaveSharedFPUModule[L] - with CanHavePTWModule +trait HasLazyRoCCModule[+L <: BaseTile with HasLazyRoCC] extends CanHavePTWModule with HasCoreParameters { this: BaseTileModule[L] => val roccCore = Wire(new RoCCCoreIO()(outer.p)) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 1b959114..de1b5641 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -6,7 +6,10 @@ package freechips.rocketchip.tile import Chisel._ import freechips.rocketchip.config._ import freechips.rocketchip.coreplex.CoreplexClockCrossing +import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ @@ -34,11 +37,47 @@ class RocketTile( (implicit p: Parameters) extends BaseTile(rocketParams, crossing)(p) with HasExternalInterrupts with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache - with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend + with HasHellaCache + with HasICacheFrontend { - nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ?? + val intOutwardNode = IntIdentityNode() + val slaveNode = TLIdentityNode() + val masterNode = TLIdentityNode() - val dtimProperty = scratch.map(d => Map( + val dtim_adapter = tileParams.dcache.flatMap { d => d.scratch.map(s => + LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO))) + } + dtim_adapter.foreach(lm => connectTLSlave(lm.node, xBytes)) + + val bus_error_unit = tileParams.core.tileControlAddr map { a => + val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a))) + intOutwardNode := beu.intNode + connectTLSlave(beu.node, xBytes) + beu + } + + val tile_master_blocker = + tileParams.blockerCtrlAddr + .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) + .map(bp => LazyModule(new BasicBusBlocker(bp))) + + tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) + + // TODO: this doesn't block other masters, e.g. RoCCs + tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } + masterNode :=* tlOtherMastersNode + tlSlaveXbar.node :*= slaveNode + + def findScratchpadFromICache: Option[AddressSet] = dtim_adapter.map { s => + val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node) + require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?") + require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!") + finalNode.get.address(0) + } + + nDCachePorts += 1 /*core */ + (dtim_adapter.isDefined).toInt + + val dtimProperty = dtim_adapter.map(d => Map( "sifive,dtim" -> d.device.asProperty)).getOrElse(Nil) val itimProperty = tileParams.icache.flatMap(_.itimAddr.map(i => Map( @@ -58,15 +97,23 @@ class RocketTile( class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer) with HasLazyRoCCModule[RocketTile] - with CanHaveScratchpadModule { + with HasHellaCacheModule + with HasICacheFrontendModule { val core = Module(p(BuildCore)(outer.p)) val uncorrectable = RegInit(Bool(false)) val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(IO(Bool(OUTPUT))) + outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem } + + outer.bus_error_unit.foreach { lm => + lm.module.io.errors.dcache := outer.dcache.module.io.errors + lm.module.io.errors.icache := outer.frontend.module.io.errors + } + outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector - outer.busErrorUnit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt } + outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt } core.io.hartid := constants.hartid // Pass through the hartid trace.foreach { _ := core.io.trace } halt_and_catch_fire.foreach { _ := uncorrectable }