riscv/rocket-chip
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ICache now returns the "next PC" signal.

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useful for other modules that need access to the fetch PC on the
   cycle it is sent to the SRAM.
This commit is contained in:
Christopher Celio 2015-05-07 04:53:05 -07:00
parent a315fe93c1
commit b09832f1b5
1 changed files with 3 additions and 1 deletions
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4
rocket/src/main/scala/icache.scala
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@ -26,7 +26,7 @@ class FrontendResp extends CoreBundle {
val xcpt_if = Bool() val xcpt_if = Bool()
} }
class CPUFrontendIO extends Bundle { class CPUFrontendIO extends CoreBundle {
val req = Valid(new FrontendReq) val req = Valid(new FrontendReq)
val resp = Decoupled(new FrontendResp).flip val resp = Decoupled(new FrontendResp).flip
val btb_resp = Valid(new BTBResp).flip val btb_resp = Valid(new BTBResp).flip
@ -34,6 +34,7 @@ class CPUFrontendIO extends Bundle {
val bht_update = Valid(new BHTUpdate) val bht_update = Valid(new BHTUpdate)
val ras_update = Valid(new RASUpdate) val ras_update = Valid(new RASUpdate)
val invalidate = Bool(OUTPUT) val invalidate = Bool(OUTPUT)
val npc = UInt(INPUT, width = vaddrBits+1)
} }
class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
@ -102,6 +103,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
icache.io.mem <> io.mem icache.io.mem <> io.mem
icache.io.req.valid := !stall && !s0_same_block icache.io.req.valid := !stall && !s0_same_block
io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
icache.io.invalidate := io.cpu.invalidate icache.io.invalidate := io.cpu.invalidate
icache.io.req.bits.ppn := tlb.io.resp.ppn icache.io.req.bits.ppn := tlb.io.resp.ppn