riscv/rocket-chip
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pass base SCR address to SCRFile for address calculation

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John Wright authored and Howard Mao committed 2016-02-24 15:32:46 -08:00
1 parent 8a877fa620
commit b04cd545b6
2 files changed
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src/main/scala/RocketChip.scala
+2 -1
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@@ -165,7 +165,8 @@ class Uncore(implicit val p: Parameters) extends Module
} }
// Arbitrate SCR access between MMIO and HTIF // Arbitrate SCR access between MMIO and HTIF
val scrFile = Module(new SCRFile("UNCORE_SCR")) val addrHashMap = new AddrHashMap(p(GlobalAddrMap), p(MMIOBase))
val scrFile = Module(new SCRFile("UNCORE_SCR",addrHashMap("conf:scr").start))
val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits)) val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
scrArb.io.in(0) <> htif.io.scr scrArb.io.in(0) <> htif.io.scr
scrArb.io.in(1) <> outmemsys.io.scr scrArb.io.in(1) <> outmemsys.io.scr
uncore
+1 -1
Submodule uncore updated: 087ed28192...e8d3518437.