From b04cd545b6fcacd51eb1aea5ec121d8409f6611a Mon Sep 17 00:00:00 2001
From: John Wright <johnwright@eecs.berkeley.edu>
Date: Mon, 22 Feb 2016 20:17:33 -0800
Subject: [PATCH] pass base SCR address to SCRFile for address calculation

---
 src/main/scala/RocketChip.scala | 3 ++-
 uncore                          | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index dab3e99c..2dcda621 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -165,7 +165,8 @@ class Uncore(implicit val p: Parameters) extends Module
   }
 
   // Arbitrate SCR access between MMIO and HTIF
-  val scrFile = Module(new SCRFile("UNCORE_SCR"))
+  val addrHashMap = new AddrHashMap(p(GlobalAddrMap), p(MMIOBase))
+  val scrFile = Module(new SCRFile("UNCORE_SCR",addrHashMap("conf:scr").start))
   val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
   scrArb.io.in(0) <> htif.io.scr
   scrArb.io.in(1) <> outmemsys.io.scr
diff --git a/uncore b/uncore
index 087ed281..e8d35184 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 087ed2819207ff0abc6bcd13b0891ba87b2a8a34
+Subproject commit e8d3518437c7cfd6544937441c9c2e758a8e48fc