riscv/rocket-chip
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pass base SCR address to SCRFile for address calculation

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John Wright 2016-02-22 20:17:33 -08:00 committed by Howard Mao
parent 8a877fa620
commit b04cd545b6
2 changed files with 3 additions and 2 deletions
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3
src/main/scala/RocketChip.scala
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@ -165,7 +165,8 @@ class Uncore(implicit val p: Parameters) extends Module
} }
// Arbitrate SCR access between MMIO and HTIF // Arbitrate SCR access between MMIO and HTIF
val scrFile = Module(new SCRFile("UNCORE_SCR")) val addrHashMap = new AddrHashMap(p(GlobalAddrMap), p(MMIOBase))
val scrFile = Module(new SCRFile("UNCORE_SCR",addrHashMap("conf:scr").start))
val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits)) val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
scrArb.io.in(0) <> htif.io.scr scrArb.io.in(0) <> htif.io.scr
scrArb.io.in(1) <> outmemsys.io.scr scrArb.io.in(1) <> outmemsys.io.scr

2
uncore

@ -1 +1 @@
Subproject commit 087ed2819207ff0abc6bcd13b0891ba87b2a8a34 Subproject commit e8d3518437c7cfd6544937441c9c2e758a8e48fc