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DebugModule: Instantiate TL2 DebugModule in BaseCoreplex

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This commit is contained in:
Megan Wachs 2016-10-24 19:01:32 -07:00 committed by Wesley W. Terpstra
parent d530ef7236
commit af924d8c51
1 changed files with 14 additions and 5 deletions
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19
src/main/scala/coreplex/BaseCoreplex.scala
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@ -48,7 +48,17 @@ case class CoreplexConfig(
val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, nInterruptPriorities)
}
abstract class BaseCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends LazyModule
abstract class BaseCoreplex(c: CoreplexConfig)(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
val debugLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
val debugModule = LazyModule(new TLDebugModule(p(XLen)/8))
debugModule.node :=
TLHintHandler()(
TLBuffer()(
TLFragmenter(p(XLen)/8, debugLegacy.tlDataBeats * debugLegacy.tlDataBytes)(
TLWidthWidget(debugLegacy.tlDataBytes)(debugLegacy.node))))
}
abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
val master = new Bundle {
@ -140,16 +150,15 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
plic.io.devices(i) <> gateway.io.plic
}
val debugModule = Module(new DebugModule)
debugModule.io.tl <> cBus.port("cbus:debug")
debugModule.io.db <> io.debug
outer.debugLegacy.module.io.legacy <> cBus.port("cbus:debug")
outer.debugModule.module.io.db <> io.debug
// connect coreplex-internal interrupts to tiles
for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
tile.interrupts <> io.clint(i)
tile.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
tile.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
tile.interrupts.debug := debugModule.io.debugInterrupts(i)
tile.interrupts.debug := outer.debugModule.module.io.debugInterrupts(i)
tile.hartid := UInt(i)
tile.resetVector := io.resetVector
}