riscv/rocket-chip
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Only instantiate div/sqrt unit if requested

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This commit is contained in:
Andrew Waterman 2015-07-22 22:17:26 -07:00
parent e9433ee01e
commit ae73e3a997
1 changed files with 4 additions and 4 deletions
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8
rocket/src/main/scala/fpu.scala
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@ -434,10 +434,8 @@ class FPU extends Module
fpmu.io.in.bits := req fpmu.io.in.bits := req
fpmu.io.lt := fpiu.io.out.bits.lt fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt = Module(new hardfloat.divSqrtRecodedFloat64)
val divSqrt_inReady = Mux(divSqrt.io.sqrtOp, divSqrt.io.inReady_sqrt, divSqrt.io.inReady_div)
val divSqrt_outValid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt
val divSqrt_wen = Reg(next=Bool(false)) val divSqrt_wen = Reg(next=Bool(false))
val divSqrt_inReady = Wire(init=Bool(false))
val divSqrt_waddr = Reg(Bits()) val divSqrt_waddr = Reg(Bits())
val divSqrt_wdata = Wire(Bits()) val divSqrt_wdata = Wire(Bits())
val divSqrt_flags = Wire(Bits()) val divSqrt_flags = Wire(Bits())
@ -512,7 +510,9 @@ class FPU extends Module
val divSqrt_flags_double = Reg(Bits()) val divSqrt_flags_double = Reg(Bits())
val divSqrt_wdata_double = Reg(Bits()) val divSqrt_wdata_double = Reg(Bits())
def upconvert(x: UInt) = hardfloat.recodedFloatNToRecodedFloatM(x, Bits(0), 23, 9, 52, 12)._1 val divSqrt = Module(new hardfloat.divSqrtRecodedFloat64)
divSqrt_inReady := Mux(divSqrt.io.sqrtOp, divSqrt.io.inReady_sqrt, divSqrt.io.inReady_div)
val divSqrt_outValid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt
val divSqrt_wb_hazard = wen.orR val divSqrt_wb_hazard = wen.orR
divSqrt.io.inValid := mem_reg_valid && !divSqrt_wb_hazard && !divSqrt_in_flight && !io.killm && (mem_ctrl.div || mem_ctrl.sqrt) divSqrt.io.inValid := mem_reg_valid && !divSqrt_wb_hazard && !divSqrt_in_flight && !io.killm && (mem_ctrl.div || mem_ctrl.sqrt)
divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.sqrtOp := mem_ctrl.sqrt