tilelink2: refactor RegField into interface and implementation
This commit is contained in:
Wesley W. Terpstra
@@ -80,138 +80,4 @@ trait HasRegMap
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def regmap(mapping: RegField.Map*): Unit
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def regmap(mapping: RegField.Map*): Unit
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}
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}
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case class RegFieldParams(indexBits: Int, maskBits: Int, extraBits: Int)
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// See GPIO.scala for an example of how to use regmap
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class RegFieldInput(params: RegFieldParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val index = UInt(width = params.indexBits)
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val data = UInt(width = params.maskBits*8)
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val mask = UInt(width = params.maskBits)
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val extra = UInt(width = params.extraBits)
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}
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class RegFieldOutput(params: RegFieldParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val data = UInt(width = params.maskBits*8)
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val extra = UInt(width = params.extraBits)
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}
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object RegFieldHelper
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{
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// Create a generic register-based device
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def apply(bytes: Int, concurrency: Option[Int], in: DecoupledIO[RegFieldInput], mapping: RegField.Map*) = {
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val regmap = mapping.toList
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require (!regmap.isEmpty)
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// Flatten the regmap into (Reg:Int, Offset:Int, field:RegField)
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val flat = regmap.map { case (reg, fields) =>
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val offsets = fields.scanLeft(0)(_ + _.width).init
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(offsets zip fields) map { case (o, f) => (reg, o, f) }
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}.flatten
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require (!flat.isEmpty)
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val endIndex = 1 << log2Ceil(regmap.map(_._1).max+1)
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val params = RegFieldParams(log2Up(endIndex), bytes, in.bits.params.extraBits)
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val out = Wire(Decoupled(new RegFieldOutput(params)))
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val front = Wire(Decoupled(new RegFieldInput(params)))
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front.bits := in.bits
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// Must this device pipeline the control channel?
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val pipelined = flat.map(_._3.pipelined).reduce(_ || _)
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val depth = concurrency.getOrElse(if (pipelined) 1 else 0)
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require (depth >= 0)
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require (!pipelined || depth > 0)
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val back = if (depth > 0) Queue(front, depth, pipe = depth == 1) else front
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// Forward declaration of all flow control signals
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val rivalid = Wire(Vec(flat.size, Bool()))
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val wivalid = Wire(Vec(flat.size, Bool()))
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val riready = Wire(Vec(flat.size, Bool()))
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val wiready = Wire(Vec(flat.size, Bool()))
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val rovalid = Wire(Vec(flat.size, Bool()))
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val wovalid = Wire(Vec(flat.size, Bool()))
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val roready = Wire(Vec(flat.size, Bool()))
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val woready = Wire(Vec(flat.size, Bool()))
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// Per-register list of all control signals needed for data to flow
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val rifire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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val wifire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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val rofire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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val wofire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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// The output values for each register
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val dataOut = Array.tabulate(endIndex) { _ => UInt(0) }
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// Which bits are touched?
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val frontMask = FillInterleaved(8, front.bits.mask)
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val backMask = FillInterleaved(8, back .bits.mask)
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// Connect the fields
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for (i <- 0 until flat.size) {
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val (reg, low, field) = flat(i)
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val high = low + field.width - 1
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// Confirm that no register is too big
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require (high <= 8*bytes)
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val rimask = frontMask(high, low).orR()
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val wimask = frontMask(high, low).andR()
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val romask = backMask(high, low).orR()
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val womask = backMask(high, low).andR()
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val data = if (field.write.combinational) back.bits.data else front.bits.data
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val (f_riready, f_rovalid, f_data) = field.read.fn(rivalid(i) && rimask, roready(i) && romask)
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val (f_wiready, f_wovalid) = field.write.fn(wivalid(i) && wimask, woready(i) && womask, data)
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riready(i) := f_riready || !rimask
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wiready(i) := f_wiready || !wimask
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rovalid(i) := f_rovalid || !romask
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wovalid(i) := f_wovalid || !womask
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rifire(reg) = riready(i) +: rifire(reg)
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wifire(reg) = wiready(i) +: wifire(reg)
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rofire(reg) = rovalid(i) +: rofire(reg)
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wofire(reg) = wovalid(i) +: wofire(reg)
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dataOut(reg) = dataOut(reg) | (f_data << low)
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}
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// Is the selected register ready?
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val rifireMux = Vec(rifire.map(_.reduce(_ && _)))
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val wifireMux = Vec(wifire.map(_.reduce(_ && _)))
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val rofireMux = Vec(rofire.map(_.reduce(_ && _)))
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val wofireMux = Vec(wofire.map(_.reduce(_ && _)))
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val iready = Mux(front.bits.read, rifireMux(front.bits.index), wifireMux(front.bits.index))
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val oready = Mux(back .bits.read, rofireMux(back .bits.index), wofireMux(back .bits.index))
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// Connect the pipeline
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in.ready := front.ready && iready
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front.valid := in.valid && iready
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back.ready := out.ready && oready
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out.valid := back.valid && oready
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// Which register is touched?
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val frontSel = UIntToOH(front.bits.index)
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val backSel = UIntToOH(back.bits.index)
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// Include the per-register one-hot selected criteria
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for (reg <- 0 until endIndex) {
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rifire(reg) = (in.valid && front.ready && front.bits.read && frontSel(reg)) +: rifire(reg)
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wifire(reg) = (in.valid && front.ready && !front.bits.read && frontSel(reg)) +: wifire(reg)
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rofire(reg) = (back.valid && out.ready && back .bits.read && backSel (reg)) +: rofire(reg)
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wofire(reg) = (back.valid && out.ready && !back .bits.read && backSel (reg)) +: wofire(reg)
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}
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// Connect the field's ivalid and oready
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for (i <- 0 until flat.size) {
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val (reg, _, _ ) = flat(i)
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rivalid(i) := rifire(reg).filter(_ ne riready(i)).reduce(_ && _)
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wivalid(i) := wifire(reg).filter(_ ne wiready(i)).reduce(_ && _)
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roready(i) := rofire(reg).filter(_ ne rovalid(i)).reduce(_ && _)
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woready(i) := wofire(reg).filter(_ ne wovalid(i)).reduce(_ && _)
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}
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out.bits.read := back.bits.read
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out.bits.data := Vec(dataOut)(back.bits.index)
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out.bits.extra := back.bits.extra
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(endIndex, out)
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}
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}
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143
uncore/src/main/scala/tilelink2/RegMapper.scala
Normal file
143
uncore/src/main/scala/tilelink2/RegMapper.scala
Normal file
@@ -0,0 +1,143 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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// A bus agnostic register interface to a register-based device
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case class RegMapperParams(indexBits: Int, maskBits: Int, extraBits: Int)
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class RegMapperInput(params: RegMapperParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val index = UInt(width = params.indexBits)
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val data = UInt(width = params.maskBits*8)
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val mask = UInt(width = params.maskBits)
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val extra = UInt(width = params.extraBits)
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}
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class RegMapperOutput(params: RegMapperParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val data = UInt(width = params.maskBits*8)
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val extra = UInt(width = params.extraBits)
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}
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object RegMapper
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{
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// Create a generic register-based device
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def apply(bytes: Int, concurrency: Option[Int], in: DecoupledIO[RegMapperInput], mapping: RegField.Map*) = {
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val regmap = mapping.toList
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require (!regmap.isEmpty)
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// Flatten the regmap into (Reg:Int, Offset:Int, field:RegField)
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val flat = regmap.map { case (reg, fields) =>
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val offsets = fields.scanLeft(0)(_ + _.width).init
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(offsets zip fields) map { case (o, f) => (reg, o, f) }
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}.flatten
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require (!flat.isEmpty)
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val endIndex = 1 << log2Ceil(regmap.map(_._1).max+1)
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val params = RegMapperParams(log2Up(endIndex), bytes, in.bits.params.extraBits)
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val out = Wire(Decoupled(new RegMapperOutput(params)))
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val front = Wire(Decoupled(new RegMapperInput(params)))
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front.bits := in.bits
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// Must this device pipeline the control channel?
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val pipelined = flat.map(_._3.pipelined).reduce(_ || _)
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val depth = concurrency.getOrElse(if (pipelined) 1 else 0)
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require (depth >= 0)
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require (!pipelined || depth > 0)
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val back = if (depth > 0) Queue(front, depth, pipe = depth == 1) else front
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// Forward declaration of all flow control signals
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val rivalid = Wire(Vec(flat.size, Bool()))
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val wivalid = Wire(Vec(flat.size, Bool()))
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val riready = Wire(Vec(flat.size, Bool()))
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val wiready = Wire(Vec(flat.size, Bool()))
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val rovalid = Wire(Vec(flat.size, Bool()))
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val wovalid = Wire(Vec(flat.size, Bool()))
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val roready = Wire(Vec(flat.size, Bool()))
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val woready = Wire(Vec(flat.size, Bool()))
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// Per-register list of all control signals needed for data to flow
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val rifire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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val wifire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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val rofire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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val wofire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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// The output values for each register
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val dataOut = Array.tabulate(endIndex) { _ => UInt(0) }
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// Which bits are touched?
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val frontMask = FillInterleaved(8, front.bits.mask)
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val backMask = FillInterleaved(8, back .bits.mask)
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// Connect the fields
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for (i <- 0 until flat.size) {
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val (reg, low, field) = flat(i)
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val high = low + field.width - 1
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// Confirm that no register is too big
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require (high <= 8*bytes)
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val rimask = frontMask(high, low).orR()
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val wimask = frontMask(high, low).andR()
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val romask = backMask(high, low).orR()
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val womask = backMask(high, low).andR()
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val data = if (field.write.combinational) back.bits.data else front.bits.data
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val (f_riready, f_rovalid, f_data) = field.read.fn(rivalid(i) && rimask, roready(i) && romask)
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val (f_wiready, f_wovalid) = field.write.fn(wivalid(i) && wimask, woready(i) && womask, data)
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riready(i) := f_riready || !rimask
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wiready(i) := f_wiready || !wimask
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rovalid(i) := f_rovalid || !romask
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wovalid(i) := f_wovalid || !womask
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rifire(reg) = riready(i) +: rifire(reg)
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wifire(reg) = wiready(i) +: wifire(reg)
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rofire(reg) = rovalid(i) +: rofire(reg)
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wofire(reg) = wovalid(i) +: wofire(reg)
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dataOut(reg) = dataOut(reg) | (f_data << low)
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}
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// Is the selected register ready?
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val rifireMux = Vec(rifire.map(_.reduce(_ && _)))
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val wifireMux = Vec(wifire.map(_.reduce(_ && _)))
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val rofireMux = Vec(rofire.map(_.reduce(_ && _)))
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val wofireMux = Vec(wofire.map(_.reduce(_ && _)))
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val iready = Mux(front.bits.read, rifireMux(front.bits.index), wifireMux(front.bits.index))
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val oready = Mux(back .bits.read, rofireMux(back .bits.index), wofireMux(back .bits.index))
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// Connect the pipeline
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in.ready := front.ready && iready
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front.valid := in.valid && iready
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back.ready := out.ready && oready
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out.valid := back.valid && oready
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// Which register is touched?
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val frontSel = UIntToOH(front.bits.index)
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val backSel = UIntToOH(back.bits.index)
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// Include the per-register one-hot selected criteria
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for (reg <- 0 until endIndex) {
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rifire(reg) = (in.valid && front.ready && front.bits.read && frontSel(reg)) +: rifire(reg)
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wifire(reg) = (in.valid && front.ready && !front.bits.read && frontSel(reg)) +: wifire(reg)
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rofire(reg) = (back.valid && out.ready && back .bits.read && backSel (reg)) +: rofire(reg)
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wofire(reg) = (back.valid && out.ready && !back .bits.read && backSel (reg)) +: wofire(reg)
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}
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// Connect the field's ivalid and oready
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for (i <- 0 until flat.size) {
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val (reg, _, _ ) = flat(i)
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rivalid(i) := rifire(reg).filter(_ ne riready(i)).reduce(_ && _)
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wivalid(i) := wifire(reg).filter(_ ne wiready(i)).reduce(_ && _)
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roready(i) := rofire(reg).filter(_ ne rovalid(i)).reduce(_ && _)
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woready(i) := wofire(reg).filter(_ ne wovalid(i)).reduce(_ && _)
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}
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out.bits.read := back.bits.read
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out.bits.data := Vec(dataOut)(back.bits.index)
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out.bits.extra := back.bits.extra
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(endIndex, out)
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}
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}
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@@ -21,8 +21,8 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
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val d = bundleIn(0).d
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val d = bundleIn(0).d
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val edge = edgesIn(0)
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val edge = edgesIn(0)
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val params = RegFieldParams(log2Up(address.mask+1), beatBytes, edge.bundle.sourceBits + edge.bundle.sizeBits)
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val params = RegMapperParams(log2Up(address.mask+1), beatBytes, edge.bundle.sourceBits + edge.bundle.sizeBits)
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val in = Wire(Decoupled(new RegFieldInput(params)))
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val in = Wire(Decoupled(new RegMapperInput(params)))
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in.bits.read := a.bits.opcode === TLMessages.Get
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in.bits.read := a.bits.opcode === TLMessages.Get
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in.bits.index := a.bits.address >> log2Ceil(beatBytes)
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in.bits.index := a.bits.address >> log2Ceil(beatBytes)
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in.bits.data := a.bits.data
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in.bits.data := a.bits.data
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@@ -30,7 +30,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
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in.bits.extra := Cat(a.bits.source, a.bits.size)
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in.bits.extra := Cat(a.bits.source, a.bits.size)
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// Invoke the register map builder
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// Invoke the register map builder
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val (endIndex, out) = RegFieldHelper(beatBytes, concurrency, in, mapping:_*)
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val (endIndex, out) = RegMapper(beatBytes, concurrency, in, mapping:_*)
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// All registers must fit inside the device address space
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// All registers must fit inside the device address space
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require (address.mask >= (endIndex-1)*beatBytes)
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require (address.mask >= (endIndex-1)*beatBytes)
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Reference in New Issue
Block a user