84 lines
2.6 KiB
Scala
84 lines
2.6 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt))
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object RegReadFn
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{
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// (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt)
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// iready may combinationally depend on oready
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// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
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// effects must become visible only on the cycle after ovalid && oready
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implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) =
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new RegReadFn(false, x)
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// (ofire: Bool) => (data: UInt)
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// effects must become visible on the cycle after ofire
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implicit def apply(x: Bool => UInt) =
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new RegReadFn(true, { case (_, oready) =>
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(Bool(true), Bool(true), x(oready))
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})
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// read from a register
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implicit def apply(x: UInt) =
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new RegReadFn(true, { case (_, _) =>
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(Bool(true), Bool(true), x)
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})
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// noop
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implicit def apply(x: Unit) =
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new RegReadFn(true, { case (_, _) =>
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(Bool(true), Bool(true), UInt(0))
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})
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}
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case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool))
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object RegWriteFn
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{
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// (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool)
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// iready may combinationally depend on both oready and data
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// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
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// effects must become visible only on the cycle after ovalid && oready
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implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) =
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new RegWriteFn(false, x)
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// (ofire: Bool, data: UInt) => ()
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// effects must become visible on the cycle after ofire
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implicit def apply(x: (Bool, UInt) => Unit) =
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new RegWriteFn(true, { case (_, oready, data) =>
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x(oready, data)
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(Bool(true), Bool(true))
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})
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// updates a register
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implicit def apply(x: UInt) =
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new RegWriteFn(true, { case (_, oready, data) =>
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when (oready) { x := data }
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(Bool(true), Bool(true))
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})
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// noop
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implicit def apply(x: Unit) =
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new RegWriteFn(true, { case (_, _, _) =>
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(Bool(true), Bool(true))
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})
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}
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case class RegField(width: Int, read: RegReadFn, write: RegWriteFn)
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{
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require (width > 0)
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def pipelined = !read.combinational || !write.combinational
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}
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object RegField
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{
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type Map = (Int, Seq[RegField])
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def apply(n: Int) : RegField = apply(n, (), ())
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def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw)
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def R(n: Int, r: RegReadFn) : RegField = apply(n, r, ())
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def W(n: Int, w: RegWriteFn) : RegField = apply(n, (), w)
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}
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trait HasRegMap
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{
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def regmap(mapping: RegField.Map*): Unit
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}
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// See GPIO.scala for an example of how to use regmap
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