riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Use chisel printf for logging

Browse Source
This commit is contained in:
Andrew Waterman 2013-06-13 10:53:23 -07:00
parent bd43ca8423
commit ae0716fb6d
5 changed files with 11 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chisel

@ -1 +1 @@
Subproject commit 2c93b2d07d54e4eaeb7aec347a3fc9f0fec5a48d Subproject commit 11cb15ba9a0f7dedf43a34e0d64708facd0ea619

36
csrc/emulator.cc
View File

@ -23,13 +23,13 @@ int main(int argc, char** argv)
uint64_t max_cycles = 0; uint64_t max_cycles = 0;
uint64_t trace_count = 0; uint64_t trace_count = 0;
int start = 0; int start = 0;
bool log = false;
const char* vcd = NULL; const char* vcd = NULL;
const char* loadmem = NULL; const char* loadmem = NULL;
FILE *vcdfile = NULL, *logfile = stderr; FILE *vcdfile = NULL;
const char* failure = NULL; const char* failure = NULL;
disassembler disasm; disassembler disasm;
bool dramsim2 = false; bool dramsim2 = false;
bool log = false;
for (int i = 1; i < argc; i++) for (int i = 1; i < argc; i++)
{ {
@ -132,39 +132,11 @@ int main(int argc, char** argv)
break; break;
} }
if (log || vcd)
{
val_t wb_reg_inst = tile.Top_Tile_core_dpath__wb_reg_inst.lo_word();
val_t wb_waddr = wb_reg_inst >> 27;
val_t wb_reg_raddr1 = (wb_reg_inst >> 22) & 0x1f;
val_t wb_reg_raddr2 = (wb_reg_inst >> 17) & 0x1f;
val_t wb_reg_rs1 = tile.Top_Tile_core_dpath__wb_reg_rs1.lo_word();
val_t wb_reg_rs2 = tile.Top_Tile_core_dpath__wb_reg_rs2.lo_word();
insn_t wb_insn;
wb_insn.bits = wb_reg_inst;
std::string wb_disasm = disasm.disassemble(wb_insn);
if (log) if (log)
{ tile.print(stderr);
fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
(long long)trace_count, tile.Top_Tile_core_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_core_dpath__wb_reg_pc.lo_word(), \
tile.Top_Tile_core_dpath__wb_reg_waddr.lo_word(), tile.Top_Tile_core_dpath__wb_wdata.lo_word(), tile.Top_Tile_core_dpath__wb_wen.lo_word(),
wb_reg_raddr1, wb_reg_rs1, wb_reg_raddr2, wb_reg_rs2, wb_reg_inst, wb_disasm.c_str());
}
if (vcd) if (vcd)
{
wb_disasm.resize(disasm_len, ' ');
dat_t<disasm_len*8> disasm_dat;
for (int i = 0; i < disasm_len; i++)
disasm_dat = disasm_dat << 8 | LIT<8>(wb_disasm[i]);
tile.dump(vcdfile, trace_count); tile.dump(vcdfile, trace_count);
dat_dump(vcdfile, disasm_dat, "NDISASM_WB");
dat_dump(vcdfile, dat_t<64>(trace_count), "NCYCLE\n");
}
}
tile.clock_hi(LIT<1>(0)); tile.clock_hi(LIT<1>(0));
trace_count++; trace_count++;
@ -183,7 +155,7 @@ int main(int argc, char** argv)
if (failure) if (failure)
{ {
fprintf(logfile, "*** FAILED *** (%s) after %lld cycles\n", failure, (long long)trace_count); fprintf(stderr, "*** FAILED *** (%s) after %lld cycles\n", failure, (long long)trace_count);
return -1; return -1;
} }

1
csrc/vcs_main.cc
View File

@ -109,6 +109,7 @@ void htif_init
void htif_fini() void htif_fini()
{ {
delete htif; delete htif;
htif = NULL;
} }
void htif_tick void htif_tick

2
riscv-rocket

@ -1 +1 @@
Subproject commit 1b6244d6bf61bebbbe9c94a9fc35e7cc414e8959 Subproject commit 23fa59e1ebc89f46f1b99d4698b4103ea6b3c1aa

2
riscv-tests

@ -1 +1 @@
Subproject commit c4e3da6be335f85482c1cbd85b6c507c48652bc8 Subproject commit 4412b96c81ca09dcce6305579dd86d4bf3b808da