From ae0716fb6d1e8dbb3d60127d4e10182c47df3a33 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 13 Jun 2013 10:53:23 -0700
Subject: [PATCH] Use chisel printf for logging

---
 chisel           |  2 +-
 csrc/emulator.cc | 42 +++++++-----------------------------------
 csrc/vcs_main.cc |  1 +
 riscv-rocket     |  2 +-
 riscv-tests      |  2 +-
 5 files changed, 11 insertions(+), 38 deletions(-)

diff --git a/chisel b/chisel
index 2c93b2d0..11cb15ba 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit 2c93b2d07d54e4eaeb7aec347a3fc9f0fec5a48d
+Subproject commit 11cb15ba9a0f7dedf43a34e0d64708facd0ea619
diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index 693120ec..d9cddacc 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -23,13 +23,13 @@ int main(int argc, char** argv)
   uint64_t max_cycles = 0;
   uint64_t trace_count = 0;
   int start = 0;
-  bool log = false;
   const char* vcd = NULL;
   const char* loadmem = NULL;
-  FILE *vcdfile = NULL, *logfile = stderr;
+  FILE *vcdfile = NULL;
   const char* failure = NULL;
   disassembler disasm;
   bool dramsim2 = false;
+  bool log = false;
 
   for (int i = 1; i < argc; i++)
   {
@@ -132,39 +132,11 @@ int main(int argc, char** argv)
       break;
     }
 
-    if (log || vcd)
-    {
-      val_t wb_reg_inst = tile.Top_Tile_core_dpath__wb_reg_inst.lo_word();
-      val_t wb_waddr = wb_reg_inst >> 27;
-      val_t wb_reg_raddr1 = (wb_reg_inst >> 22) & 0x1f;
-      val_t wb_reg_raddr2 = (wb_reg_inst >> 17) & 0x1f;
-      val_t wb_reg_rs1 =  tile.Top_Tile_core_dpath__wb_reg_rs1.lo_word();
-      val_t wb_reg_rs2 =  tile.Top_Tile_core_dpath__wb_reg_rs2.lo_word();
+    if (log)
+      tile.print(stderr);
 
-      insn_t wb_insn;
-      wb_insn.bits = wb_reg_inst;
-      std::string wb_disasm = disasm.disassemble(wb_insn);
-      
-      if (log)
-      {
-        fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
-                (long long)trace_count, tile.Top_Tile_core_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_core_dpath__wb_reg_pc.lo_word(), \
-                tile.Top_Tile_core_dpath__wb_reg_waddr.lo_word(), tile.Top_Tile_core_dpath__wb_wdata.lo_word(), tile.Top_Tile_core_dpath__wb_wen.lo_word(),
-                wb_reg_raddr1, wb_reg_rs1, wb_reg_raddr2, wb_reg_rs2, wb_reg_inst, wb_disasm.c_str());
-      }
-
-      if (vcd)
-      {
-        wb_disasm.resize(disasm_len, ' ');
-        dat_t<disasm_len*8> disasm_dat;
-        for (int i = 0; i < disasm_len; i++)
-          disasm_dat = disasm_dat << 8 | LIT<8>(wb_disasm[i]);
-
-        tile.dump(vcdfile, trace_count);
-        dat_dump(vcdfile, disasm_dat, "NDISASM_WB");
-        dat_dump(vcdfile, dat_t<64>(trace_count), "NCYCLE\n");
-      }
-    }
+    if (vcd)
+      tile.dump(vcdfile, trace_count);
 
     tile.clock_hi(LIT<1>(0));
     trace_count++;
@@ -183,7 +155,7 @@ int main(int argc, char** argv)
 
   if (failure)
   {
-    fprintf(logfile, "*** FAILED *** (%s) after %lld cycles\n", failure, (long long)trace_count);
+    fprintf(stderr, "*** FAILED *** (%s) after %lld cycles\n", failure, (long long)trace_count);
     return -1;
   }
 
diff --git a/csrc/vcs_main.cc b/csrc/vcs_main.cc
index e5f5162b..7c5151b5 100644
--- a/csrc/vcs_main.cc
+++ b/csrc/vcs_main.cc
@@ -109,6 +109,7 @@ void htif_init
 void htif_fini()
 {
   delete htif;
+  htif = NULL;
 }
 
 void htif_tick
diff --git a/riscv-rocket b/riscv-rocket
index 1b6244d6..23fa59e1 160000
--- a/riscv-rocket
+++ b/riscv-rocket
@@ -1 +1 @@
-Subproject commit 1b6244d6bf61bebbbe9c94a9fc35e7cc414e8959
+Subproject commit 23fa59e1ebc89f46f1b99d4698b4103ea6b3c1aa
diff --git a/riscv-tests b/riscv-tests
index c4e3da6b..4412b96c 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit c4e3da6be335f85482c1cbd85b6c507c48652bc8
+Subproject commit 4412b96c81ca09dcce6305579dd86d4bf3b808da