riscv/rocket-chip
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Removed all traces of params

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This commit is contained in:
Henry Cook 2015-10-05 20:33:55 -07:00
parent 970445a26a
commit adcd77db36
8 changed files with 182 additions and 180 deletions
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107
junctions/src/main/scala/addrmap.scala Normal file
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@ -0,0 +1,107 @@
// See LICENSE for license details.
package junctions
import Chisel._
import scala.collection.mutable.HashMap
abstract class MemRegion { def size: BigInt }
case class MemSize(size: BigInt, prot: Int) extends MemRegion
case class MemSubmap(size: BigInt, entries: AddrMap) extends MemRegion
object AddrMapConsts {
val R = 0x4
val W = 0x2
val X = 0x1
val RW = R | W
val RX = R | X
val RWX = R | W | X
}
class AddrMapProt extends Bundle {
val r = Bool()
val w = Bool()
val x = Bool()
}
case class AddrMapEntry(name: String, start: Option[BigInt], region: MemRegion)
case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int)
class AddrMap(entries: Seq[AddrMapEntry]) extends scala.collection.IndexedSeq[AddrMapEntry] {
def apply(index: Int): AddrMapEntry = entries(index)
def length: Int = entries.size
def countSlaves: Int = {
this map { entry: AddrMapEntry => entry.region match {
case MemSize(_, _) => 1
case MemSubmap(_, submap) => submap.countSlaves
}} reduceLeft(_ + _)
}
}
object AddrMap {
def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems)
}
class AddrHashMap(addrmap: AddrMap) {
val mapping = new HashMap[String, AddrHashMapEntry]
private def genPairs(am: AddrMap): Seq[(String, AddrHashMapEntry)] = {
var ind = 0
var base = BigInt(0)
var pairs = Seq[(String, AddrHashMapEntry)]()
am.foreach { case AddrMapEntry(name, startOpt, region) =>
region match {
case MemSize(size, prot) => {
if (!startOpt.isEmpty) base = startOpt.get
pairs = (name, AddrHashMapEntry(ind, base, size, prot)) +: pairs
base += size
ind += 1
}
case MemSubmap(size, submap) => {
if (!startOpt.isEmpty) base = startOpt.get
val subpairs = genPairs(submap).map {
case (subname, AddrHashMapEntry(subind, subbase, subsize, prot)) =>
(name + ":" + subname,
AddrHashMapEntry(ind + subind, base + subbase, subsize, prot))
}
pairs = subpairs ++ pairs
ind += subpairs.size
base += size
}
}
}
pairs
}
for ((name, ind) <- genPairs(addrmap)) { mapping(name) = ind }
def nEntries: Int = mapping.size
def apply(name: String): AddrHashMapEntry = mapping(name)
def get(name: String): Option[AddrHashMapEntry] = mapping.get(name)
def sortedEntries(): Seq[(String, BigInt, BigInt, Int)] = {
val arr = new Array[(String, BigInt, BigInt, Int)](mapping.size)
mapping.foreach { case (name, AddrHashMapEntry(port, base, size, prot)) =>
arr(port) = (name, base, size, prot)
}
arr.toSeq
}
def isValid(addr: UInt): Bool = {
sortedEntries().map { case (_, base, size, _) =>
addr >= UInt(base) && addr < UInt(base + size)
}.reduceLeft(_ || _)
}
def getProt(addr: UInt): AddrMapProt = {
Mux1H(sortedEntries().map { case (_, base, size, prot) =>
(addr >= UInt(base) && addr < UInt(base + size),
new AddrMapProt().fromBits(Bits(prot, 3)))
})
}
}

74
junctions/src/main/scala/hasti.scala
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@ -2,7 +2,7 @@ package junctions
import Chisel._
abstract trait HASTIConstants
trait HastiConstants
{
val SZ_HTRANS = 2
val HTRANS_IDLE = UInt(0, SZ_HTRANS)
@ -27,16 +27,22 @@ abstract trait HASTIConstants
val SZ_HSIZE = 3
val SZ_HPROT = 4
// TODO: Parameterize
val SZ_HADDR = 32
val SZ_HDATA = 32
def dgate(valid: Bool, b: UInt) = Fill(b.getWidth, valid) & b
}
class HASTIMasterIO extends Bundle
{
val haddr = UInt(OUTPUT, SZ_HADDR)
trait HasHastiParameters {
implicit val p: Parameters
val hastiAddrBits = 32
val hastiDataBits = 32
}
abstract class HastiModule(implicit val p: Parameters) extends Module
with HasHastiParameters
abstract class HastiBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasHastiParameters
class HastiMasterIO(implicit p: Parameters) extends HastiBundle()(p) {
val haddr = UInt(OUTPUT, hastiAddrBits)
val hwrite = Bool(OUTPUT)
val hsize = UInt(OUTPUT, SZ_HSIZE)
val hburst = UInt(OUTPUT, SZ_HBURST)
@ -44,16 +50,15 @@ class HASTIMasterIO extends Bundle
val htrans = UInt(OUTPUT, SZ_HTRANS)
val hmastlock = Bool(OUTPUT)
val hwdata = Bits(OUTPUT, SZ_HDATA)
val hrdata = Bits(INPUT, SZ_HDATA)
val hwdata = Bits(OUTPUT, hastiDataBits)
val hrdata = Bits(INPUT, hastiDataBits)
val hready = Bool(INPUT)
val hresp = UInt(INPUT, SZ_HRESP)
}
class HASTISlaveIO extends Bundle
{
val haddr = UInt(INPUT, SZ_HADDR)
class HastiSlaveIO(implicit p: Parameters) extends HastiBundle()(p) {
val haddr = UInt(INPUT, hastiAddrBits)
val hwrite = Bool(INPUT)
val hsize = UInt(INPUT, SZ_HSIZE)
val hburst = UInt(INPUT, SZ_HBURST)
@ -61,8 +66,8 @@ class HASTISlaveIO extends Bundle
val htrans = UInt(INPUT, SZ_HTRANS)
val hmastlock = Bool(INPUT)
val hwdata = Bits(INPUT, SZ_HDATA)
val hrdata = Bits(OUTPUT, SZ_HDATA)
val hwdata = Bits(INPUT, hastiDataBits)
val hrdata = Bits(OUTPUT, hastiDataBits)
val hsel = Bool(INPUT)
val hreadyin = Bool(INPUT)
@ -70,23 +75,22 @@ class HASTISlaveIO extends Bundle
val hresp = UInt(OUTPUT, SZ_HRESP)
}
class HASTIBus(amap: Seq[UInt=>Bool]) extends Module
{
class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p) {
val io = new Bundle {
val master = new HASTIMasterIO().flip
val slaves = Vec(new HASTISlaveIO, amap.size).flip
val master = new HastiMasterIO().flip
val slaves = Vec(new HastiSlaveIO, amap.size).flip
}
// skid buffer
val skb_valid = Reg(init = Bool(false))
val skb_haddr = Reg(UInt(width = SZ_HADDR))
val skb_haddr = Reg(UInt(width = hastiAddrBits))
val skb_hwrite = Reg(Bool())
val skb_hsize = Reg(UInt(width = SZ_HSIZE))
val skb_hburst = Reg(UInt(width = SZ_HBURST))
val skb_hprot = Reg(UInt(width = SZ_HPROT))
val skb_htrans = Reg(UInt(width = SZ_HTRANS))
val skb_hmastlock = Reg(Bool())
val skb_hwdata = Reg(UInt(width = SZ_HDATA))
val skb_hwdata = Reg(UInt(width = hastiDataBits))
val master_haddr = Mux(skb_valid, skb_haddr, io.master.haddr)
val master_hwrite = Mux(skb_valid, skb_hwrite, io.master.hwrite)
@ -142,16 +146,15 @@ class HASTIBus(amap: Seq[UInt=>Bool]) extends Module
io.master.hresp := Mux1H(s1_hsels, io.slaves.map(_.hresp))
}
class HASTISlaveMux(n: Int) extends Module
{
class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
val io = new Bundle {
val ins = Vec(new HASTISlaveIO, n)
val out = new HASTISlaveIO().flip
val ins = Vec(new HastiSlaveIO, n)
val out = new HastiSlaveIO().flip
}
// skid buffers
val skb_valid = Array.fill(n){Reg(init = Bool(false))}
val skb_haddr = Array.fill(n){Reg(UInt(width = SZ_HADDR))}
val skb_haddr = Array.fill(n){Reg(UInt(width = hastiAddrBits))}
val skb_hwrite = Array.fill(n){Reg(Bool())}
val skb_hsize = Array.fill(n){Reg(UInt(width = SZ_HSIZE))}
val skb_hburst = Array.fill(n){Reg(UInt(width = SZ_HBURST))}
@ -212,15 +215,15 @@ class HASTISlaveMux(n: Int) extends Module
} }
}
class HASTIXbar(nMasters: Int, addressMap: Seq[UInt=>Bool]) extends Module
{
class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])
(implicit p: Parameters) extends HastiModule()(p) {
val io = new Bundle {
val masters = Vec(new HASTIMasterIO, nMasters).flip
val slaves = Vec(new HASTISlaveIO, addressMap.size).flip
val masters = Vec(new HastiMasterIO, nMasters).flip
val slaves = Vec(new HastiSlaveIO, addressMap.size).flip
}
val buses = List.fill(nMasters){Module(new HASTIBus(addressMap))}
val muxes = List.fill(addressMap.size){Module(new HASTISlaveMux(nMasters))}
val buses = List.fill(nMasters){Module(new HastiBus(addressMap))}
val muxes = List.fill(addressMap.size){Module(new HastiSlaveMux(nMasters))}
(buses.map(b => b.io.master) zip io.masters) foreach { case (b, m) => b <> m }
(muxes.map(m => m.io.out) zip io.slaves ) foreach { case (x, s) => x <> s }
@ -229,11 +232,10 @@ class HASTIXbar(nMasters: Int, addressMap: Seq[UInt=>Bool]) extends Module
}
}
class HASTISlaveToMaster extends Module
{
class HastiSlaveToMaster(implicit p: Parameters) extends HastiModule()(p) {
val io = new Bundle {
val in = new HASTISlaveIO
val out = new HASTIMasterIO
val in = new HastiSlaveIO
val out = new HastiMasterIO
}
io.out.haddr := io.in.haddr

18
junctions/src/main/scala/memserdes.scala
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@ -26,8 +26,8 @@ trait HasMIFParameters {
val mifDataBeats = p(MIFDataBeats)
}
abstract class MIFModule extends Module with HasMIFParameters
abstract class MIFBundle(implicit p: Parameters) extends ParameterizedBundle()(p)
abstract class MIFModule(implicit val p: Parameters) extends Module with HasMIFParameters
abstract class MIFBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasMIFParameters
trait HasMemData extends HasMIFParameters {
@ -46,9 +46,9 @@ class MemReqCmd(implicit p: Parameters) extends MIFBundle()(p) with HasMemAddr w
val rw = Bool()
}
class MemTag(implicit p: Parameters) extends ParameterizedBundle()(p) with HasMemTag
class MemData(implicit p: Parameters) extends ParameterizedBundle()(p) with HasMemData
class MemResp(implicit p: Parameters) extends ParameterizedBundle()(p) with HasMemData with HasMemTag
class MemTag(implicit p: Parameters) extends MIFBundle()(p) with HasMemTag
class MemData(implicit p: Parameters) extends MIFBundle()(p) with HasMemData
class MemResp(implicit p: Parameters) extends MIFBundle()(p) with HasMemData with HasMemTag
class MemIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
val req_cmd = Decoupled(new MemReqCmd)
@ -68,7 +68,7 @@ class MemSerializedIO(w: Int)(implicit p: Parameters) extends ParameterizedBundl
//override def cloneType = new MemSerializedIO(w)(p).asInstanceOf[this.type]
}
class MemSerdes(w: Int)(implicit val p: Parameters) extends MIFModule
class MemSerdes(w: Int)(implicit p: Parameters) extends MIFModule
{
val io = new Bundle {
val wide = new MemIO().flip
@ -154,7 +154,7 @@ class MemDesser(w: Int)(implicit p: Parameters) extends Module // test rig side
val abits = io.wide.req_cmd.bits.toBits.getWidth
val dbits = io.wide.req_data.bits.toBits.getWidth
val rbits = io.wide.resp.bits.getWidth
val mifDataBeats = params(MIFDataBeats)
val mifDataBeats = p(MIFDataBeats)
require(dbits >= abits && rbits >= dbits)
val recv_cnt = Reg(init=UInt(0, log2Up((rbits+w-1)/w)))
@ -214,7 +214,7 @@ class MemDesser(w: Int)(implicit p: Parameters) extends Module // test rig side
io.narrow.resp.bits := dataq.io.deq.bits.toBits >> (recv_cnt * UInt(w))
}
class MemIOArbiter(val arbN: Int)(implicit val p: Parameters) extends MIFModule {
class MemIOArbiter(val arbN: Int)(implicit p: Parameters) extends MIFModule {
val io = new Bundle {
val inner = Vec(new MemIO, arbN).flip
val outer = new MemIO
@ -273,7 +273,7 @@ object MemIOMemPipeIOConverter {
}
}
class MemPipeIOMemIOConverter(numRequests: Int)(implicit val p: Parameters) extends MIFModule {
class MemPipeIOMemIOConverter(numRequests: Int)(implicit p: Parameters) extends MIFModule {
val io = new Bundle {
val cpu = new MemIO().flip
val mem = new MemPipeIO

136
junctions/src/main/scala/nasti.scala
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@ -4,9 +4,8 @@ package junctions
import Chisel._
import scala.math.max
import scala.collection.mutable.ArraySeq
import scala.collection.mutable.HashMap
case object NastiBitWidths extends Field[NastiParameters]
case object NastiKey extends Field[NastiParameters]
case object NastiAddrMap extends Field[AddrMap]
case object MMIOBase extends Field[BigInt]
@ -14,7 +13,7 @@ case class NastiParameters(dataBits: Int, addrBits: Int, idBits: Int)
trait HasNastiParameters {
implicit val p: Parameters
val external = p(NastiBitWidths)
val external = p(NastiKey)
val nastiXDataBits = external.dataBits
val nastiWStrobeBits = nastiXDataBits / 8
val nastiXAddrBits = external.addrBits
@ -47,8 +46,9 @@ trait HasNastiParameters {
UInt(128) -> UInt(7)))
}
abstract class NastiModule extends Module with HasNastiParameters
abstract class NastiBundle(implicit p: Parameters) extends ParameterizedBundle()(p)
abstract class NastiModule(implicit val p: Parameters) extends Module
with HasNastiParameters
abstract class NastiBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasNastiParameters
abstract class NastiChannel(implicit p: Parameters) extends NastiBundle()(p)
@ -72,7 +72,7 @@ trait HasNastiData extends HasNastiParameters {
val last = Bool()
}
class NastiIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
class NastiIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
val aw = Decoupled(new NastiWriteAddressChannel)
val w = Decoupled(new NastiWriteDataChannel)
val b = Decoupled(new NastiWriteResponseChannel).flip
@ -190,7 +190,7 @@ object NastiWriteResponseChannel {
}
}
class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit val p: Parameters) extends MIFModule
class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit p: Parameters) extends MIFModule
with HasNastiParameters {
val io = new Bundle {
val nasti = (new NastiIO).flip
@ -245,7 +245,7 @@ class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit val p: Parameter
}
/** Arbitrate among arbN masters requesting to a single slave */
class NastiArbiter(val arbN: Int)(implicit val p: Parameters) extends NastiModule {
class NastiArbiter(val arbN: Int)(implicit p: Parameters) extends NastiModule {
val io = new Bundle {
val master = Vec(new NastiIO, arbN).flip
val slave = new NastiIO
@ -315,7 +315,7 @@ class NastiArbiter(val arbN: Int)(implicit val p: Parameters) extends NastiModul
/** Locking RR arbiter for Nasti read data channel
* Arbiter locks until last message in channel is sent */
class NastiReadDataArbiter(arbN: Int)(implicit val p: Parameters) extends NastiModule {
class NastiReadDataArbiter(arbN: Int)(implicit p: Parameters) extends NastiModule {
val io = new Bundle {
val in = Vec(Decoupled(new NastiReadDataChannel), arbN).flip
val out = Decoupled(new NastiReadDataChannel)
@ -356,7 +356,7 @@ class NastiReadDataArbiter(arbN: Int)(implicit val p: Parameters) extends NastiM
}
/** A slave that send decode error for every request it receives */
class NastiErrorSlave(implicit val p: Parameters) extends NastiModule {
class NastiErrorSlave(implicit p: Parameters) extends NastiModule {
val io = (new NastiIO).flip
when (io.ar.fire()) { printf("Invalid read address %x\n", io.ar.bits.addr) }
@ -408,7 +408,7 @@ class NastiErrorSlave(implicit val p: Parameters) extends NastiModule {
/** Take a single Nasti master and route its requests to various slaves
* @param addrmap a sequence of base address + memory size pairs,
* on for each slave interface */
class NastiRouter(addrmap: Seq[(BigInt, BigInt)])(implicit val p: Parameters) extends NastiModule {
class NastiRouter(addrmap: Seq[(BigInt, BigInt)])(implicit p: Parameters) extends NastiModule {
val nSlaves = addrmap.size
val io = new Bundle {
@ -488,7 +488,7 @@ class NastiRouter(addrmap: Seq[(BigInt, BigInt)])(implicit val p: Parameters) ex
* @param addrmap a sequence of base - size pairs;
* size of addrmap should be nSlaves */
class NastiCrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
(implicit val p: Parameters) extends NastiModule {
(implicit p: Parameters) extends NastiModule {
val io = new Bundle {
val masters = Vec(new NastiIO, nMasters).flip
val slaves = Vec(new NastiIO, nSlaves)
@ -507,112 +507,6 @@ class NastiCrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
}
}
object AddrMapConsts {
val R = 0x4
val W = 0x2
val X = 0x1
val RW = R | W
val RX = R | X
val RWX = R | W | X
}
class AddrMapProt extends Bundle {
val r = Bool()
val w = Bool()
val x = Bool()
}
abstract class MemRegion { def size: BigInt }
case class MemSize(size: BigInt, prot: Int) extends MemRegion
case class MemSubmap(size: BigInt, entries: AddrMap) extends MemRegion
//object Submap {
// def apply(size: BigInt, entries: AddrMapEntry*) =
// new MemSubmap(size, entries)
//}
case class AddrMapEntry(name: String, start: Option[BigInt], region: MemRegion)
case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int)
class AddrMap(entries: Seq[AddrMapEntry]) extends scala.collection.IndexedSeq[AddrMapEntry] {
def apply(index: Int): AddrMapEntry = entries(index)
def length: Int = entries.size
def countSlaves: Int = {
this map { entry: AddrMapEntry => entry.region match {
case MemSize(_, _) => 1
case MemSubmap(_, submap) => submap.countSlaves
}} reduceLeft(_ + _)
}
}
object AddrMap {
def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems)
}
class AddrHashMap(addrmap: AddrMap) {
val mapping = new HashMap[String, AddrHashMapEntry]
private def genPairs(am: AddrMap): Seq[(String, AddrHashMapEntry)] = {
var ind = 0
var base = BigInt(0)
var pairs = Seq[(String, AddrHashMapEntry)]()
am.foreach { case AddrMapEntry(name, startOpt, region) =>
region match {
case MemSize(size, prot) => {
if (!startOpt.isEmpty) base = startOpt.get
pairs = (name, AddrHashMapEntry(ind, base, size, prot)) +: pairs
base += size
ind += 1
}
case MemSubmap(size, submap) => {
if (!startOpt.isEmpty) base = startOpt.get
val subpairs = genPairs(submap).map {
case (subname, AddrHashMapEntry(subind, subbase, subsize, prot)) =>
(name + ":" + subname,
AddrHashMapEntry(ind + subind, base + subbase, subsize, prot))
}
pairs = subpairs ++ pairs
ind += subpairs.size
base += size
}
}
}
pairs
}
for ((name, ind) <- genPairs(addrmap)) { mapping(name) = ind }
def nEntries: Int = mapping.size
def apply(name: String): AddrHashMapEntry = mapping(name)
def get(name: String): Option[AddrHashMapEntry] = mapping.get(name)
def sortedEntries(): Seq[(String, BigInt, BigInt, Int)] = {
val arr = new Array[(String, BigInt, BigInt, Int)](mapping.size)
mapping.foreach { case (name, AddrHashMapEntry(port, base, size, prot)) =>
arr(port) = (name, base, size, prot)
}
arr.toSeq
}
def isValid(addr: UInt): Bool = {
sortedEntries().map { case (_, base, size, _) =>
addr >= UInt(base) && addr < UInt(base + size)
}.reduceLeft(_ || _)
}
def getProt(addr: UInt): AddrMapProt = {
Mux1H(sortedEntries().map { case (_, base, size, prot) =>
(addr >= UInt(base) && addr < UInt(base + size),
new AddrMapProt().fromBits(Bits(prot, 3)))
})
}
}
class NastiInterconnectIO(val nMasters: Int, val nSlaves: Int)
(implicit p: Parameters) extends Bundle {
/* This is a bit confusing. The interconnect is a slave to the masters and
@ -623,7 +517,7 @@ class NastiInterconnectIO(val nMasters: Int, val nSlaves: Int)
new NastiInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
}
abstract class NastiInterconnect extends NastiModule {
abstract class NastiInterconnect(implicit p: Parameters) extends NastiModule()(p) {
val nMasters: Int
val nSlaves: Int
@ -635,7 +529,7 @@ class NastiRecursiveInterconnect(
val nSlaves: Int,
addrmap: AddrMap,
base: BigInt = 0)
(implicit val p: Parameters) extends NastiInterconnect {
(implicit p: Parameters) extends NastiInterconnect {
var lastEnd = base
var slaveInd = 0
val levelSize = addrmap.size
@ -678,7 +572,7 @@ class NastiRecursiveInterconnect(
}
class NastiTopInterconnect(val nMasters: Int, val nSlaves: Int)
(implicit val p: Parameters) extends NastiInterconnect {
(implicit p: Parameters) extends NastiInterconnect {
val temp = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, p(NastiAddrMap)))
temp.io.masters.zip(io.masters).foreach { case (t, i) =>

2
junctions/src/main/scala/package.scala
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@ -1 +1 @@
package object junctions extends HASTIConstants with POCIConstants
package object junctions extends HastiConstants with PociConstants

17
junctions/src/main/scala/poci.scala
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@ -2,13 +2,13 @@ package junctions
import Chisel._
abstract trait POCIConstants
abstract trait PociConstants
{
val SZ_PADDR = 32
val SZ_PDATA = 32
}
class POCIIO extends Bundle
class PociIO extends Bundle
{
val paddr = UInt(OUTPUT, SZ_PADDR)
val pwrite = Bool(OUTPUT)
@ -20,11 +20,10 @@ class POCIIO extends Bundle
val pslverr = Bool(INPUT)
}
class HASTItoPOCIBridge extends Module
{
class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
val io = new Bundle {
val in = new HASTISlaveIO
val out = new POCIIO
val in = new HastiSlaveIO
val out = new PociIO
}
val s_idle :: s_setup :: s_access :: Nil = Enum(UInt(), 3)
@ -62,11 +61,11 @@ class HASTItoPOCIBridge extends Module
io.in.hresp := io.out.pslverr
}
class POCIBus(amap: Seq[UInt=>Bool]) extends Module
class PociBus(amap: Seq[UInt=>Bool]) extends Module
{
val io = new Bundle {
val master = new POCIIO().flip
val slaves = Vec(new POCIIO, amap.size)
val master = new PociIO().flip
val slaves = Vec(new PociIO, amap.size)
}
val psels = PriorityEncoderOH(

6
junctions/src/main/scala/smi.scala
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@ -88,7 +88,7 @@ class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
}
class SMIIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
(implicit val p: Parameters) extends NastiModule {
(implicit p: Parameters) extends NastiModule()(p) {
val io = new Bundle {
val ar = Decoupled(new NastiReadAddressChannel).flip
val r = Decoupled(new NastiReadDataChannel)
@ -170,7 +170,7 @@ class SMIIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
}
class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
(implicit val p: Parameters) extends NastiModule {
(implicit p: Parameters) extends NastiModule()(p) {
val io = new Bundle {
val aw = Decoupled(new NastiWriteAddressChannel).flip
val w = Decoupled(new NastiWriteDataChannel).flip
@ -251,7 +251,7 @@ class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
/** Convert Nasti protocol to SMI protocol */
class SMIIONastiIOConverter(val dataWidth: Int, val addrWidth: Int)
(implicit val p: Parameters) extends NastiModule {
(implicit p: Parameters) extends NastiModule()(p) {
val io = new Bundle {
val nasti = (new NastiIO).flip
val smi = new SMIIO(dataWidth, addrWidth)

2
junctions/src/main/scala/util.scala
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@ -6,7 +6,7 @@ object bigIntPow2 {
def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0)
}
class ParameterizedBundle(implicit val p: Parameters) extends Bundle {
class ParameterizedBundle(implicit p: Parameters) extends Bundle {
override def cloneType = this.getClass.getConstructors.head.newInstance(p).asInstanceOf[this.type]
}