326 lines
11 KiB
Scala
326 lines
11 KiB
Scala
// See LICENSE for license details.
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package junctions
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import Chisel._
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import scala.math._
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case object PAddrBits extends Field[Int]
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case object VAddrBits extends Field[Int]
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case object PgIdxBits extends Field[Int]
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case object PgLevels extends Field[Int]
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case object PgLevelBits extends Field[Int]
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case object ASIdBits extends Field[Int]
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case object PPNBits extends Field[Int]
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case object VPNBits extends Field[Int]
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case object MIFAddrBits extends Field[Int]
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case object MIFDataBits extends Field[Int]
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case object MIFTagBits extends Field[Int]
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case object MIFDataBeats extends Field[Int]
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trait HasMIFParameters {
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implicit val p: Parameters
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val mifTagBits = p(MIFTagBits)
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val mifAddrBits = p(MIFAddrBits)
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val mifDataBits = p(MIFDataBits)
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val mifDataBeats = p(MIFDataBeats)
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}
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abstract class MIFModule(implicit val p: Parameters) extends Module with HasMIFParameters
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abstract class MIFBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasMIFParameters
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trait HasMemData extends HasMIFParameters {
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val data = Bits(width = mifDataBits)
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}
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trait HasMemAddr extends HasMIFParameters {
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val addr = UInt(width = mifAddrBits)
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}
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trait HasMemTag extends HasMIFParameters {
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val tag = UInt(width = mifTagBits)
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}
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class MemReqCmd(implicit p: Parameters) extends MIFBundle()(p) with HasMemAddr with HasMemTag {
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val rw = Bool()
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}
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class MemTag(implicit p: Parameters) extends MIFBundle()(p) with HasMemTag
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class MemData(implicit p: Parameters) extends MIFBundle()(p) with HasMemData
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class MemResp(implicit p: Parameters) extends MIFBundle()(p) with HasMemData with HasMemTag
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class MemIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val req_cmd = Decoupled(new MemReqCmd)
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val req_data = Decoupled(new MemData)
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val resp = Decoupled(new MemResp).flip
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}
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class MemPipeIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val req_cmd = Decoupled(new MemReqCmd)
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val req_data = Decoupled(new MemData)
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val resp = Valid(new MemResp).flip
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}
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class MemSerializedIO(w: Int)(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val req = Decoupled(Bits(width = w))
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val resp = Valid(Bits(width = w)).flip
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//override def cloneType = new MemSerializedIO(w)(p).asInstanceOf[this.type]
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}
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class MemSerdes(w: Int)(implicit p: Parameters) extends MIFModule
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{
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val io = new Bundle {
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val wide = new MemIO().flip
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val narrow = new MemSerializedIO(w)
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}
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val abits = io.wide.req_cmd.bits.toBits.getWidth
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val dbits = io.wide.req_data.bits.toBits.getWidth
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val rbits = io.wide.resp.bits.getWidth
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val out_buf = Reg(Bits())
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val in_buf = Reg(Bits())
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val s_idle :: s_read_addr :: s_write_addr :: s_write_idle :: s_write_data :: Nil = Enum(UInt(), 5)
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val state = Reg(init=s_idle)
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val send_cnt = Reg(init=UInt(0, log2Up((max(abits, dbits)+w-1)/w)))
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val data_send_cnt = Reg(init=UInt(0, log2Up(mifDataBeats)))
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val adone = io.narrow.req.ready && send_cnt === UInt((abits-1)/w)
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val ddone = io.narrow.req.ready && send_cnt === UInt((dbits-1)/w)
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when (io.narrow.req.valid && io.narrow.req.ready) {
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send_cnt := send_cnt + UInt(1)
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out_buf := out_buf >> UInt(w)
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}
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when (io.wide.req_cmd.valid && io.wide.req_cmd.ready) {
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out_buf := io.wide.req_cmd.bits.toBits
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}
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when (io.wide.req_data.valid && io.wide.req_data.ready) {
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out_buf := io.wide.req_data.bits.toBits
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}
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io.wide.req_cmd.ready := state === s_idle
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io.wide.req_data.ready := state === s_write_idle
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io.narrow.req.valid := state === s_read_addr || state === s_write_addr || state === s_write_data
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io.narrow.req.bits := out_buf
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when (state === s_idle && io.wide.req_cmd.valid) {
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state := Mux(io.wide.req_cmd.bits.rw, s_write_addr, s_read_addr)
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}
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when (state === s_read_addr && adone) {
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state := s_idle
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send_cnt := UInt(0)
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}
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when (state === s_write_addr && adone) {
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state := s_write_idle
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send_cnt := UInt(0)
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}
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when (state === s_write_idle && io.wide.req_data.valid) {
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state := s_write_data
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}
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when (state === s_write_data && ddone) {
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data_send_cnt := data_send_cnt + UInt(1)
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state := Mux(data_send_cnt === UInt(mifDataBeats-1), s_idle, s_write_idle)
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send_cnt := UInt(0)
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}
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val recv_cnt = Reg(init=UInt(0, log2Up((rbits+w-1)/w)))
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val data_recv_cnt = Reg(init=UInt(0, log2Up(mifDataBeats)))
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val resp_val = Reg(init=Bool(false))
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resp_val := Bool(false)
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when (io.narrow.resp.valid) {
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recv_cnt := recv_cnt + UInt(1)
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when (recv_cnt === UInt((rbits-1)/w)) {
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recv_cnt := UInt(0)
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data_recv_cnt := data_recv_cnt + UInt(1)
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resp_val := Bool(true)
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}
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in_buf := Cat(io.narrow.resp.bits, in_buf((rbits+w-1)/w*w-1,w))
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}
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io.wide.resp.valid := resp_val
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io.wide.resp.bits := io.wide.resp.bits.fromBits(in_buf)
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}
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class MemDesserIO(w: Int)(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val narrow = new MemSerializedIO(w).flip
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val wide = new MemIO
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}
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class MemDesser(w: Int)(implicit p: Parameters) extends Module // test rig side
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{
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val io = new MemDesserIO(w)
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val abits = io.wide.req_cmd.bits.toBits.getWidth
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val dbits = io.wide.req_data.bits.toBits.getWidth
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val rbits = io.wide.resp.bits.getWidth
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val mifDataBeats = p(MIFDataBeats)
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require(dbits >= abits && rbits >= dbits)
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val recv_cnt = Reg(init=UInt(0, log2Up((rbits+w-1)/w)))
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val data_recv_cnt = Reg(init=UInt(0, log2Up(mifDataBeats)))
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val adone = io.narrow.req.valid && recv_cnt === UInt((abits-1)/w)
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val ddone = io.narrow.req.valid && recv_cnt === UInt((dbits-1)/w)
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val rdone = io.narrow.resp.valid && recv_cnt === UInt((rbits-1)/w)
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val s_cmd_recv :: s_cmd :: s_data_recv :: s_data :: s_reply :: Nil = Enum(UInt(), 5)
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val state = Reg(init=s_cmd_recv)
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val in_buf = Reg(Bits())
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when (io.narrow.req.valid && io.narrow.req.ready || io.narrow.resp.valid) {
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recv_cnt := recv_cnt + UInt(1)
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in_buf := Cat(io.narrow.req.bits, in_buf((rbits+w-1)/w*w-1,w))
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}
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io.narrow.req.ready := state === s_cmd_recv || state === s_data_recv
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when (state === s_cmd_recv && adone) {
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state := s_cmd
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recv_cnt := UInt(0)
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}
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when (state === s_cmd && io.wide.req_cmd.ready) {
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state := Mux(io.wide.req_cmd.bits.rw, s_data_recv, s_reply)
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}
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when (state === s_data_recv && ddone) {
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state := s_data
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recv_cnt := UInt(0)
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}
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when (state === s_data && io.wide.req_data.ready) {
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state := s_data_recv
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when (data_recv_cnt === UInt(mifDataBeats-1)) {
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state := s_cmd_recv
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}
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data_recv_cnt := data_recv_cnt + UInt(1)
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}
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when (rdone) { // state === s_reply
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when (data_recv_cnt === UInt(mifDataBeats-1)) {
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state := s_cmd_recv
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}
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recv_cnt := UInt(0)
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data_recv_cnt := data_recv_cnt + UInt(1)
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}
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val req_cmd = in_buf >> UInt(((rbits+w-1)/w - (abits+w-1)/w)*w)
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io.wide.req_cmd.valid := state === s_cmd
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io.wide.req_cmd.bits := io.wide.req_cmd.bits.fromBits(req_cmd)
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io.wide.req_data.valid := state === s_data
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io.wide.req_data.bits.data := in_buf >> UInt(((rbits+w-1)/w - (dbits+w-1)/w)*w)
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val dataq = Module(new Queue(new MemResp, mifDataBeats))
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dataq.io.enq <> io.wide.resp
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dataq.io.deq.ready := recv_cnt === UInt((rbits-1)/w)
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io.narrow.resp.valid := dataq.io.deq.valid
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io.narrow.resp.bits := dataq.io.deq.bits.toBits >> (recv_cnt * UInt(w))
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}
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class MemIOArbiter(val arbN: Int)(implicit p: Parameters) extends MIFModule {
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val io = new Bundle {
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val inner = Vec(new MemIO, arbN).flip
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val outer = new MemIO
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}
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if(arbN > 1) {
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val cmd_arb = Module(new RRArbiter(new MemReqCmd, arbN))
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val choice_q = Module(new Queue(cmd_arb.io.chosen, 4))
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val (data_cnt, data_done) = Counter(io.outer.req_data.fire(), mifDataBeats)
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io.inner.map(_.req_cmd).zipWithIndex.zip(cmd_arb.io.in).map{ case ((req, id), arb) => {
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arb.valid := req.valid
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arb.bits := req.bits
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arb.bits.tag := Cat(req.bits.tag, UInt(id))
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req.ready := arb.ready
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}}
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io.outer.req_cmd.bits := cmd_arb.io.out.bits
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io.outer.req_cmd.valid := cmd_arb.io.out.valid && choice_q.io.enq.ready
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cmd_arb.io.out.ready := io.outer.req_cmd.ready && choice_q.io.enq.ready
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choice_q.io.enq.bits := cmd_arb.io.chosen
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choice_q.io.enq.valid := cmd_arb.io.out.fire() && cmd_arb.io.out.bits.rw
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io.outer.req_data.bits := io.inner(choice_q.io.deq.bits).req_data.bits
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io.outer.req_data.valid := io.inner(choice_q.io.deq.bits).req_data.valid && choice_q.io.deq.valid
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io.inner.map(_.req_data.ready).zipWithIndex.foreach {
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case(r, i) => r := UInt(i) === choice_q.io.deq.bits && choice_q.io.deq.valid
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}
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choice_q.io.deq.ready := data_done
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io.outer.resp.ready := Bool(false)
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for (i <- 0 until arbN) {
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io.inner(i).resp.valid := Bool(false)
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when(io.outer.resp.bits.tag(log2Up(arbN)-1,0).toUInt === UInt(i)) {
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io.inner(i).resp.valid := io.outer.resp.valid
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io.outer.resp.ready := io.inner(i).resp.ready
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}
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io.inner(i).resp.bits := io.outer.resp.bits
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io.inner(i).resp.bits.tag := io.outer.resp.bits.tag >> UInt(log2Up(arbN))
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}
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} else { io.outer <> io.inner.head }
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}
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object MemIOMemPipeIOConverter {
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def apply(in: MemPipeIO)(implicit p: Parameters): MemIO = {
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val out = Wire(new MemIO())
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in.resp.valid := out.resp.valid
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in.resp.bits := out.resp.bits
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out.resp.ready := Bool(true)
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out.req_cmd.valid := in.req_cmd.valid
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out.req_cmd.bits := in.req_cmd.bits
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in.req_cmd.ready := out.req_cmd.ready
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out.req_data.valid := in.req_data.valid
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out.req_data.bits := in.req_data.bits
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in.req_data.ready := out.req_data.ready
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out
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}
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}
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class MemPipeIOMemIOConverter(numRequests: Int)(implicit p: Parameters) extends MIFModule {
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val io = new Bundle {
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val cpu = new MemIO().flip
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val mem = new MemPipeIO
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}
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val numEntries = numRequests * mifDataBeats
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val size = log2Down(numEntries) + 1
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val inc = Wire(Bool())
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val dec = Wire(Bool())
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val count = Reg(init=UInt(numEntries, size))
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val watermark = count >= UInt(mifDataBeats)
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when (inc && !dec) {
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count := count + UInt(1)
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}
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when (!inc && dec) {
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count := count - UInt(mifDataBeats)
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}
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when (inc && dec) {
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count := count - UInt(mifDataBeats-1)
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}
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val cmdq_mask = io.cpu.req_cmd.bits.rw || watermark
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io.mem.req_cmd.valid := io.cpu.req_cmd.valid && cmdq_mask
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io.cpu.req_cmd.ready := io.mem.req_cmd.ready && cmdq_mask
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io.mem.req_cmd.bits := io.cpu.req_cmd.bits
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io.mem.req_data <> io.cpu.req_data
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// Have separate queues to allow for different mem implementations
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val resp_data_q = Module((new HellaQueue(numEntries)) { new MemData })
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resp_data_q.io.enq.valid := io.mem.resp.valid
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resp_data_q.io.enq.bits.data := io.mem.resp.bits.data
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val resp_tag_q = Module((new HellaQueue(numEntries)) { new MemTag })
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resp_tag_q.io.enq.valid := io.mem.resp.valid
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resp_tag_q.io.enq.bits.tag := io.mem.resp.bits.tag
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io.cpu.resp.valid := resp_data_q.io.deq.valid && resp_tag_q.io.deq.valid
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io.cpu.resp.bits.data := resp_data_q.io.deq.bits.data
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io.cpu.resp.bits.tag := resp_tag_q.io.deq.bits.tag
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resp_data_q.io.deq.ready := io.cpu.resp.ready
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resp_tag_q.io.deq.ready := io.cpu.resp.ready
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inc := resp_data_q.io.deq.fire() && resp_tag_q.io.deq.fire()
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dec := io.mem.req_cmd.fire() && !io.mem.req_cmd.bits.rw
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}
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