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Changes to prepare for switch to TileLink interconnect

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We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.

* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
This commit is contained in:
Howard Mao
2016-03-28 13:22:00 -07:00
parent 5378f79b50
commit ad93e0226d
5 changed files with 30 additions and 48 deletions
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13
src/main/scala/TestConfigs.scala
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@ -17,12 +17,11 @@ class WithGroundTest extends Config(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NTiles),
nCachelessClients = site(NTiles) + (if (site(UseDma)) 2 else 1),
maxClientXacts = max_int(site(NMSHRs) + 1,
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts),
if (site(UseDma)) 4 else 1),
maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2,
if (site(UseDma)) site(NDmaTransactors) + 1 else 1),
nCachelessClients = site(NTiles) + site(ExtraL1Clients),
maxClientXacts = max(
site(NMSHRs) + 1,
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBits = site(CacheBlockBytes)*8)
case BuildTiles => {
@ -81,7 +80,6 @@ class WithCacheRegressionTest extends Config(
class WithDmaTest extends Config(
(pname, site, here) => pname match {
case UseDma => true
case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new DmaTest()(p))
case DmaTestSet => DmaTestCases(
@ -97,7 +95,6 @@ class WithDmaTest extends Config(
class WithDmaStreamTest extends Config(
(pname, site, here) => pname match {
case UseDma => true
case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new DmaStreamTest()(p))
case DmaStreamTestSettings => DmaStreamTestConfig(