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Changes to prepare for switch to TileLink interconnect

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We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.

* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
This commit is contained in:
Howard Mao
2016-03-28 13:22:00 -07:00
parent 5378f79b50
commit ad93e0226d
5 changed files with 30 additions and 48 deletions
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28
src/main/scala/RocketChip.scala
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@ -33,10 +33,10 @@ case object UseHtifClockDiv extends Field[Boolean]
case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
/** Function for building some kind of tile connected to a reset signal */
case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
/** Enable DMA engine */
case object UseDma extends Field[Boolean]
/** A string describing on-chip devices, readable by target software */
case object ConfigString extends cde.Field[Array[Byte]]
case object ConfigString extends Field[Array[Byte]]
/** Number of L1 clients besides the CPU cores */
case object ExtraL1Clients extends Field[Int]
case object UseStreamLoopback extends Field[Boolean]
case object StreamLoopbackSize extends Field[Int]
@ -45,11 +45,10 @@ case object StreamLoopbackWidth extends Field[Int]
/** Utility trait for quick access to some relevant parameters */
trait HasTopLevelParameters {
implicit val p: Parameters
lazy val useDma = p(UseDma)
lazy val nTiles = p(NTiles)
lazy val nCachedTilePorts = p(TLKey("L1toL2")).nCachingClients
lazy val nUncachedTilePorts =
p(TLKey("L1toL2")).nCachelessClients - (if (useDma) 2 else 1)
p(TLKey("L1toL2")).nCachelessClients - p(ExtraL1Clients)
lazy val htifW = p(HtifKey).width
lazy val csrAddrBits = 12
lazy val nMemChannels = p(NMemoryChannels)
@ -222,17 +221,15 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val deviceTree = new NastiIO
}
val dmaOpt = if (p(UseDma))
Some(Module(new DmaEngine(
DmaCtrlRegNumbers.CSR_BASE + DmaCtrlRegNumbers.OUTSTANDING)))
else None
val mmioBase = p(MMIOBase)
val rtc = Module(new RTC(CSRs.mtime))
// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
// Cached ports are first in client list, making sharerToClientId just an indentity function
// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
val ordered_clients = (io.tiles_cached ++
(io.tiles_uncached ++ dmaOpt.map(_.io.mem) :+ io.htif_uncached)
(io.tiles_uncached ++ Seq(rtc.io, io.htif_uncached))
.map(TileLinkIOWrapper(_)))
def sharerToClientId(sharerId: UInt) = sharerId
def addrToBank(addr: Bits): UInt = {
@ -254,6 +251,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
case OuterTLId => "L2toMC"
})))
// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
// and coherence manager(s) to the other side
l1tol2net.io.clients <> ordered_clients
@ -266,7 +264,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val addrMap = p(GlobalAddrMap)
val addrHashMap = new AddrHashMap(addrMap, mmioBase)
val nMasters = (if (dmaOpt.isEmpty) 2 else 3)
val nSlaves = addrHashMap.nEntries
// TODO: the code to print this stuff should live somewhere else
@ -277,7 +274,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
println("Generated Configuration String")
println(new String(p(ConfigString)))
val mmio_ic = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, addrMap, mmioBase))
val mmio_ic = Module(new NastiRecursiveInterconnect(1, nSlaves, addrMap, mmioBase))
val channelConfigs = p(MemoryChannelMuxConfigs)
require(channelConfigs.sortWith(_ > _)(0) == nMemChannels,
@ -309,13 +306,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
mmio_conv.io.tl <> mmio_narrow.io.out
TopUtils.connectNasti(mmio_ic.io.masters(0), mmio_conv.io.nasti)
val rtc = Module(new RTC(CSRs.mtime))
mmio_ic.io.masters(1) <> rtc.io
dmaOpt.foreach { dma =>
mmio_ic.io.masters(2) <> dma.io.mmio
dma.io.ctrl <> mmio_ic.io.slaves(addrHashMap("devices:dma").port)
}
for (i <- 0 until nTiles) {
val csrName = s"conf:csr$i"