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Revert "Don't rely on Mux1H output when no inputs are hot"

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This reverts commit b912b7cd1263d7f3b63e6fcb052d9d7493d1b970.
This commit is contained in:
Wesley W. Terpstra 2016-06-08 13:39:22 -07:00
parent 3393d4362b
commit ad4e4f19be
1 changed files with 2 additions and 5 deletions
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7
junctions/src/main/scala/hasti.scala
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@ -273,23 +273,20 @@ class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])(implicit p: Paramete
diversions(m).io.divert := bubbleM(m) && NSeq(m) && masters(m).hready diversions(m).io.divert := bubbleM(m) && NSeq(m) && masters(m).hready
} }
def dotProduct(g: Seq[Bool], v: Seq[UInt]) =
(g zip v) map { case (gg, ss) => Mux(gg, ss, ss.fromBits(UInt(0))) } reduce (_|_)
// Master muxes (address and data phase are the same) // Master muxes (address and data phase are the same)
(masters zip (unionGrantMS zip nowhereM)) foreach { case (m, (g, n)) => { (masters zip (unionGrantMS zip nowhereM)) foreach { case (m, (g, n)) => {
// If the master is connected to a slave, the slave determines hready. // If the master is connected to a slave, the slave determines hready.
// However, if no slave is connected, for progress report ready anyway, if: // However, if no slave is connected, for progress report ready anyway, if:
// bad address (swallow request) OR idle (permit stupid slaves to move FSM) // bad address (swallow request) OR idle (permit stupid slaves to move FSM)
val autoready = n || m.isIdle() val autoready = n || m.isIdle()
m.hready := dotProduct(g, slaves.map(_.hready ^ autoready)) ^ autoready m.hready := Mux1H(g, slaves.map(_.hready ^ autoready)) ^ autoready
m.hrdata := Mux1H(g, slaves.map(_.hrdata)) m.hrdata := Mux1H(g, slaves.map(_.hrdata))
m.hresp := Mux1H(g, slaves.map(_.hresp)) m.hresp := Mux1H(g, slaves.map(_.hresp))
} } } }
// Slave address phase muxes // Slave address phase muxes
(slaves zip addressPhaseGrantSM) foreach { case (s, g) => { (slaves zip addressPhaseGrantSM) foreach { case (s, g) => {
s.htrans := dotProduct(g, masters.map(_.htrans)) // defaults to HTRANS_IDLE (0) s.htrans := Mux1H(g, masters.map(_.htrans)) // defaults to HTRANS_IDLE (0)
s.haddr := Mux1H(g, masters.map(_.haddr)) s.haddr := Mux1H(g, masters.map(_.haddr))
s.hmastlock := isLocked s.hmastlock := isLocked
s.hwrite := Mux1H(g, masters.map(_.hwrite)) s.hwrite := Mux1H(g, masters.map(_.hwrite))