riscv/rocket-chip
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rocketchip: reduce number of type parameters

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This commit is contained in:
Wesley W. Terpstra
2016-10-28 16:47:20 -07:00
parent 043ed48c8c
commit ac886026e6
5 changed files with 16 additions and 14 deletions
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7
src/main/scala/coreplex/BaseCoreplex.scala
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@@ -75,7 +75,8 @@ abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bund
val success = Bool(OUTPUT) // used for testing
}
abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) with HasCoreplexParameters {
abstract class BareCoreplexModule[+B <: BareCoreplexBundle[BareCoreplex]](val io: B) extends LazyModuleImp(io.outer) with HasCoreplexParameters {
val outer = io.outer.asInstanceOf[io.outer.type]
implicit val p = outer.p
// Create and export the ConfigString
@@ -200,11 +201,11 @@ trait CoreplexPeripheralsModule extends HasCoreplexParameters {
class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
with CoreplexPeripherals {
override lazy val module = new BaseCoreplexModule(this, new BaseCoreplexBundle(this))
override lazy val module = new BaseCoreplexModule(new BaseCoreplexBundle(this))
}
class BaseCoreplexBundle[+L <: BaseCoreplex](outer: L) extends BareCoreplexBundle(outer)
with CoreplexPeripheralsBundle
class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle[L]](outer: L, io: B) extends BareCoreplexModule(outer, io)
class BaseCoreplexModule[+B <: BaseCoreplexBundle[BaseCoreplex]](io: B) extends BareCoreplexModule(io)
with CoreplexPeripheralsModule

8
src/main/scala/coreplex/Coreplex.scala
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@@ -39,12 +39,12 @@ trait DirectConnectionModule {
class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
with DirectConnection {
override lazy val module = new DefaultCoreplexModule(this, new DefaultCoreplexBundle(this))
override lazy val module = new DefaultCoreplexModule(new DefaultCoreplexBundle(this))
}
class DefaultCoreplexBundle[+L <: DefaultCoreplex](outer: L) extends BaseCoreplexBundle(outer)
class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
class DefaultCoreplexModule[+B <: DefaultCoreplexBundle[DefaultCoreplex]](io: B) extends BaseCoreplexModule(io)
with DirectConnectionModule
/////
@@ -111,11 +111,11 @@ trait AsyncConnectionModule extends Module {
class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
with AsyncConnection {
override lazy val module = new MultiClockCoreplexModule(this, new MultiClockCoreplexBundle(this))
override lazy val module = new MultiClockCoreplexModule(new MultiClockCoreplexBundle(this))
}
class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](outer: L) extends BaseCoreplexBundle(outer)
with TileClockResetBundle
class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
class MultiClockCoreplexModule[+B <: MultiClockCoreplexBundle[MultiClockCoreplex]](io: B) extends BaseCoreplexModule(io)
with AsyncConnectionModule

4
src/main/scala/groundtest/Coreplex.scala
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@@ -6,12 +6,12 @@ import coreplex._
class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
with DirectConnection {
override lazy val module = new GroundTestCoreplexModule(this, new GroundTestCoreplexBundle(this))
override lazy val module = new GroundTestCoreplexModule(new GroundTestCoreplexBundle(this))
}
class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](outer: L) extends BaseCoreplexBundle(outer)
class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
class GroundTestCoreplexModule[+B <: GroundTestCoreplexBundle[GroundTestCoreplex]](io: B) extends BaseCoreplexModule(io)
with DirectConnectionModule {
io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
}

3
src/main/scala/rocketchip/BaseTop.scala
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@@ -57,7 +57,8 @@ abstract class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](val outer: L) extends
val success = Bool(OUTPUT)
}
abstract class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) {
abstract class BaseTopModule[+B <: BaseTopBundle[BaseTop[BaseCoreplex]]](val io: B) extends LazyModuleImp(io.outer) {
val outer = io.outer.asInstanceOf[io.outer.type]
implicit val p = outer.p
val coreplexMem : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem)

8
src/main/scala/rocketchip/ExampleTop.scala
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@@ -17,7 +17,7 @@ class ExampleTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p:
with PeripheryMasterAXI4MMIO
with PeripherySlave
with DirectConnection {
override lazy val module = new ExampleTopModule(this, new ExampleTopBundle(this))
override lazy val module = new ExampleTopModule(new ExampleTopBundle(this))
}
class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](outer: L) extends BaseTopBundle(outer)
@@ -28,7 +28,7 @@ class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](outer: L) extends BaseTop
with PeripheryMasterAXI4MMIOBundle
with PeripherySlaveBundle
class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](outer: L, io: B) extends BaseTopModule(outer, io)
class ExampleTopModule[+B <: ExampleTopBundle[ExampleTop[BaseCoreplex]]](io: B) extends BaseTopModule(io)
with PeripheryBootROMModule
with PeripheryDebugModule
with PeripheryExtInterruptsModule
@@ -41,11 +41,11 @@ class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]
/** Example Top with TestRAM */
class ExampleTopWithTestRAM[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(buildCoreplex)
with PeripheryTestRAM {
override lazy val module = new ExampleTopWithTestRAMModule(this, new ExampleTopWithTestRAMBundle(this))
override lazy val module = new ExampleTopWithTestRAMModule(new ExampleTopWithTestRAMBundle(this))
}
class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](outer: L) extends ExampleTopBundle(outer)
with PeripheryTestRAMBundle
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM[BaseCoreplex], +B <: ExampleTopWithTestRAMBundle[L]](outer: L, io: B) extends ExampleTopModule(outer, io)
class ExampleTopWithTestRAMModule[+B <: ExampleTopWithTestRAMBundle[ExampleTopWithTestRAM[BaseCoreplex]]](io: B) extends ExampleTopModule(io)
with PeripheryTestRAMModule