From ac886026e69474cbf03eec7dad9c28b83f85bb60 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 28 Oct 2016 16:47:20 -0700 Subject: [PATCH] rocketchip: reduce number of type parameters --- src/main/scala/coreplex/BaseCoreplex.scala | 7 ++++--- src/main/scala/coreplex/Coreplex.scala | 8 ++++---- src/main/scala/groundtest/Coreplex.scala | 4 ++-- src/main/scala/rocketchip/BaseTop.scala | 3 ++- src/main/scala/rocketchip/ExampleTop.scala | 8 ++++---- 5 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index dead46fe..c79db428 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -75,7 +75,8 @@ abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bund val success = Bool(OUTPUT) // used for testing } -abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) with HasCoreplexParameters { +abstract class BareCoreplexModule[+B <: BareCoreplexBundle[BareCoreplex]](val io: B) extends LazyModuleImp(io.outer) with HasCoreplexParameters { + val outer = io.outer.asInstanceOf[io.outer.type] implicit val p = outer.p // Create and export the ConfigString @@ -200,11 +201,11 @@ trait CoreplexPeripheralsModule extends HasCoreplexParameters { class BaseCoreplex(implicit p: Parameters) extends BareCoreplex with CoreplexPeripherals { - override lazy val module = new BaseCoreplexModule(this, new BaseCoreplexBundle(this)) + override lazy val module = new BaseCoreplexModule(new BaseCoreplexBundle(this)) } class BaseCoreplexBundle[+L <: BaseCoreplex](outer: L) extends BareCoreplexBundle(outer) with CoreplexPeripheralsBundle -class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle[L]](outer: L, io: B) extends BareCoreplexModule(outer, io) +class BaseCoreplexModule[+B <: BaseCoreplexBundle[BaseCoreplex]](io: B) extends BareCoreplexModule(io) with CoreplexPeripheralsModule diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index 6f98b144..062ce597 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -39,12 +39,12 @@ trait DirectConnectionModule { class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex with DirectConnection { - override lazy val module = new DefaultCoreplexModule(this, new DefaultCoreplexBundle(this)) + override lazy val module = new DefaultCoreplexModule(new DefaultCoreplexBundle(this)) } class DefaultCoreplexBundle[+L <: DefaultCoreplex](outer: L) extends BaseCoreplexBundle(outer) -class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io) +class DefaultCoreplexModule[+B <: DefaultCoreplexBundle[DefaultCoreplex]](io: B) extends BaseCoreplexModule(io) with DirectConnectionModule ///// @@ -111,11 +111,11 @@ trait AsyncConnectionModule extends Module { class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex with AsyncConnection { - override lazy val module = new MultiClockCoreplexModule(this, new MultiClockCoreplexBundle(this)) + override lazy val module = new MultiClockCoreplexModule(new MultiClockCoreplexBundle(this)) } class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](outer: L) extends BaseCoreplexBundle(outer) with TileClockResetBundle -class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io) +class MultiClockCoreplexModule[+B <: MultiClockCoreplexBundle[MultiClockCoreplex]](io: B) extends BaseCoreplexModule(io) with AsyncConnectionModule diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index 59310230..04cb2650 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -6,12 +6,12 @@ import coreplex._ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex with DirectConnection { - override lazy val module = new GroundTestCoreplexModule(this, new GroundTestCoreplexBundle(this)) + override lazy val module = new GroundTestCoreplexModule(new GroundTestCoreplexBundle(this)) } class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](outer: L) extends BaseCoreplexBundle(outer) -class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io) +class GroundTestCoreplexModule[+B <: GroundTestCoreplexBundle[GroundTestCoreplex]](io: B) extends BaseCoreplexModule(io) with DirectConnectionModule { io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_) } diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index 813a5af0..de2e8720 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -57,7 +57,8 @@ abstract class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](val outer: L) extends val success = Bool(OUTPUT) } -abstract class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) { +abstract class BaseTopModule[+B <: BaseTopBundle[BaseTop[BaseCoreplex]]](val io: B) extends LazyModuleImp(io.outer) { + val outer = io.outer.asInstanceOf[io.outer.type] implicit val p = outer.p val coreplexMem : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem) diff --git a/src/main/scala/rocketchip/ExampleTop.scala b/src/main/scala/rocketchip/ExampleTop.scala index f128b415..847781bf 100644 --- a/src/main/scala/rocketchip/ExampleTop.scala +++ b/src/main/scala/rocketchip/ExampleTop.scala @@ -17,7 +17,7 @@ class ExampleTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: with PeripheryMasterAXI4MMIO with PeripherySlave with DirectConnection { - override lazy val module = new ExampleTopModule(this, new ExampleTopBundle(this)) + override lazy val module = new ExampleTopModule(new ExampleTopBundle(this)) } class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](outer: L) extends BaseTopBundle(outer) @@ -28,7 +28,7 @@ class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](outer: L) extends BaseTop with PeripheryMasterAXI4MMIOBundle with PeripherySlaveBundle -class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](outer: L, io: B) extends BaseTopModule(outer, io) +class ExampleTopModule[+B <: ExampleTopBundle[ExampleTop[BaseCoreplex]]](io: B) extends BaseTopModule(io) with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule @@ -41,11 +41,11 @@ class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L] /** Example Top with TestRAM */ class ExampleTopWithTestRAM[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(buildCoreplex) with PeripheryTestRAM { - override lazy val module = new ExampleTopWithTestRAMModule(this, new ExampleTopWithTestRAMBundle(this)) + override lazy val module = new ExampleTopWithTestRAMModule(new ExampleTopWithTestRAMBundle(this)) } class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](outer: L) extends ExampleTopBundle(outer) with PeripheryTestRAMBundle -class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM[BaseCoreplex], +B <: ExampleTopWithTestRAMBundle[L]](outer: L, io: B) extends ExampleTopModule(outer, io) +class ExampleTopWithTestRAMModule[+B <: ExampleTopWithTestRAMBundle[ExampleTopWithTestRAM[BaseCoreplex]]](io: B) extends ExampleTopModule(io) with PeripheryTestRAMModule