riscv/rocket-chip
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rocketchip: reduce number of type parameters

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This commit is contained in:
Wesley W. Terpstra
2016-10-28 16:47:20 -07:00
parent 043ed48c8c
commit ac886026e6
5 changed files with 16 additions and 14 deletions
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3
src/main/scala/rocketchip/BaseTop.scala
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@@ -57,7 +57,8 @@ abstract class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](val outer: L) extends
val success = Bool(OUTPUT)
}
abstract class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) {
abstract class BaseTopModule[+B <: BaseTopBundle[BaseTop[BaseCoreplex]]](val io: B) extends LazyModuleImp(io.outer) {
val outer = io.outer.asInstanceOf[io.outer.type]
implicit val p = outer.p
val coreplexMem : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem)