riscv/rocket-chip
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rocketchip: reduce number of type parameters

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This commit is contained in:
Wesley W. Terpstra
2016-10-28 16:47:20 -07:00
parent 043ed48c8c
commit ac886026e6
5 changed files with 16 additions and 14 deletions
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8
src/main/scala/coreplex/Coreplex.scala
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@ -39,12 +39,12 @@ trait DirectConnectionModule {
class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
with DirectConnection {
override lazy val module = new DefaultCoreplexModule(this, new DefaultCoreplexBundle(this))
override lazy val module = new DefaultCoreplexModule(new DefaultCoreplexBundle(this))
}
class DefaultCoreplexBundle[+L <: DefaultCoreplex](outer: L) extends BaseCoreplexBundle(outer)
class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
class DefaultCoreplexModule[+B <: DefaultCoreplexBundle[DefaultCoreplex]](io: B) extends BaseCoreplexModule(io)
with DirectConnectionModule
/////
@ -111,11 +111,11 @@ trait AsyncConnectionModule extends Module {
class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
with AsyncConnection {
override lazy val module = new MultiClockCoreplexModule(this, new MultiClockCoreplexBundle(this))
override lazy val module = new MultiClockCoreplexModule(new MultiClockCoreplexBundle(this))
}
class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](outer: L) extends BaseCoreplexBundle(outer)
with TileClockResetBundle
class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
class MultiClockCoreplexModule[+B <: MultiClockCoreplexBundle[MultiClockCoreplex]](io: B) extends BaseCoreplexModule(io)
with AsyncConnectionModule