riscv/rocket-chip
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print out core id

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This commit is contained in:
Yunsup Lee 2014-03-04 23:38:49 -08:00
parent 9f2e16c58a
commit ac4b3f9f22
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/dpath.scala
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@ -300,8 +300,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
io.ctrl.mem_waddr := mem_reg_inst(11,7) io.ctrl.mem_waddr := mem_reg_inst(11,7)
io.ctrl.wb_waddr := wb_reg_inst(11,7) io.ctrl.wb_waddr := wb_reg_inst(11,7)
printf("C: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
pcr.io.time(32,0), io.ctrl.retire, wb_reg_pc, io.host.id, pcr.io.time(32,0), io.ctrl.retire, wb_reg_pc,
Mux(wb_wen, wb_waddr, UInt(0)), wb_wdata, wb_wen, Mux(wb_wen, wb_waddr, UInt(0)), wb_wdata, wb_wen,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))), wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))), wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),