cleanup DirectoryRepresentation and coherence params
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@ -123,7 +123,7 @@ object L2Metadata {
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}
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}
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class L2Metadata extends Metadata with L2HellaCacheParameters {
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val coh = new MasterMetadata()(co) //co.masterMetadataOnFlush.clone
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val coh = new MasterMetadata
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}
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class L2MetaReadReq extends MetaReadReq with HasL2Id {
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@ -524,8 +524,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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val (local_data_resp_cnt, local_data_resp_done) = Counter(io.data.resp.valid, tlDataBeats)
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val release_count = Reg(init = UInt(0, width = log2Up(nClients+1)))
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val pending_probes = Reg(init = co.dir().flush)
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val curr_p_id = co.dir().next(pending_probes)
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val pending_probes = Reg(init = co.dir.flush)
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val curr_p_id = co.dir.next(pending_probes)
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val needs_writeback = !xact_tag_match && co.needsWriteback(xact_meta.coh)
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val is_hit = xact_tag_match && co.isHit(xact, xact_meta.coh)
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@ -645,11 +645,11 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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val _is_hit = _tag_match && co.isHit(xact, coh)
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val _needs_probes = co.requiresProbes(xact, coh)
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when(_needs_probes) {
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val mask_incoherent = co.dir().full(coh.sharers) & ~io.tile_incoherent
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val mask_incoherent = co.dir.full(coh.sharers) & ~io.tile_incoherent
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val mask_self = mask_incoherent &
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~(!(co.requiresSelfProbe(xact) || _needs_writeback) << xact_src)
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pending_probes := mask_self
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release_count := co.dir().count(mask_self)
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release_count := co.dir.count(mask_self)
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crel_had_data := Bool(false)
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crel_was_voluntary := Bool(false)
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}
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@ -663,9 +663,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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}
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}
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is(s_probe) {
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io.inner.probe.valid := !co.dir().none(pending_probes)
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io.inner.probe.valid := !co.dir.none(pending_probes)
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when(io.inner.probe.ready) {
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pending_probes := co.dir().pop(pending_probes, curr_p_id)
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pending_probes := co.dir.pop(pending_probes, curr_p_id)
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}
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// Handle releases, which may have data being written back
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