riscv/rocket-chip
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get rid of vxcptwait

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This commit is contained in:
Yunsup Lee 2012-03-21 15:08:48 -07:00
parent 023734175d
commit aaed0241af
5 changed files with 183 additions and 128 deletions
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2
rocket/src/main/scala/cpu.scala
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@ -209,8 +209,6 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
// exceptions // exceptions
vu.io.xcpt.exception := ctrl.io.vec_iface.exception vu.io.xcpt.exception := ctrl.io.vec_iface.exception
ctrl.io.vec_iface.exception_ack_valid := vu.io.xcpt.exception_ack_valid
vu.io.xcpt.exception_ack_ready := ctrl.io.vec_iface.exception_ack_ready
vu.io.xcpt.evac := ctrl.io.vec_iface.evac vu.io.xcpt.evac := ctrl.io.vec_iface.evac
vu.io.xcpt.evac_addr := dpath.io.vec_iface.evac_addr.toUFix vu.io.xcpt.evac_addr := dpath.io.vec_iface.evac_addr.toUFix
vu.io.xcpt.kill := ctrl.io.vec_iface.kill vu.io.xcpt.kill := ctrl.io.vec_iface.kill

32
rocket/src/main/scala/ctrl.scala
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@ -97,7 +97,7 @@ object rocketCtrlDecode
val xpr64 = Y; val xpr64 = Y;
val decode_default = val decode_default =
// vfence_cv // vfence
// | eret // | eret
// | | syscall // | | syscall
// vec_val mem_val mul_val div_val renpcr | | | privileged // vec_val mem_val mul_val div_val renpcr | | | privileged
@ -106,7 +106,7 @@ object rocketCtrlDecode
List(N, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N) List(N, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N)
val xdecode = Array( val xdecode = Array(
// vfence_cv // vfence
// | eret // | eret
// | | syscall // | | syscall
// vec_val mem_val mul_val div_val renpcr | | | privileged // vec_val mem_val mul_val div_val renpcr | | | privileged
@ -215,7 +215,7 @@ object rocketCtrlDecode
RDINSTRET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_IRT,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N)) RDINSTRET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_IRT,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N))
val fdecode = Array( val fdecode = Array(
// vfence_cv // vfence
// | eret // | eret
// | | syscall // | | syscall
// vec_val mem_val mul_val div_val renpcr | | | privileged // vec_val mem_val mul_val div_val renpcr | | | privileged
@ -255,7 +255,7 @@ object rocketCtrlDecode
FSD-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N)) FSD-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N))
val vdecode = Array( val vdecode = Array(
// vfence_cv // vfence
// | eret // | eret
// | | syscall // | | syscall
// vec_val mem_val mul_val div_val renpcr | | | privileged // vec_val mem_val mul_val div_val renpcr | | | privileged
@ -307,7 +307,6 @@ object rocketCtrlDecode
VENQCNT-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), VENQCNT-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
VXCPTEVAC-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), VXCPTEVAC-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
VXCPTKILL-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), VXCPTKILL-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
VXCPTWAIT-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,Y),
VXCPTHOLD-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N)) VXCPTHOLD-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N))
} }
@ -323,7 +322,7 @@ class rocketCtrl extends Component
val id_int_val :: id_vec_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs val id_int_val :: id_vec_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0 val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0
val id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_vfence_cv :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1 val id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_vfence :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false)); val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false));
@ -445,8 +444,26 @@ class rocketCtrl extends Component
vec.io.exception := wb_reg_exception vec.io.exception := wb_reg_exception
vec.io.eret := wb_reg_eret vec.io.eret := wb_reg_eret
val vec_dec = new rocketCtrlVecDecoder()
vec_dec.io.inst := io.dpath.inst
val s = io.dpath.status(SR_S)
val mask_cmdq_ready = !vec_dec.io.sigs.enq_cmdq || s && io.vec_iface.vcmdq_ready || !s && io.vec_iface.vcmdq_user_ready
val mask_ximm1q_ready = !vec_dec.io.sigs.enq_ximm1q || s && io.vec_iface.vximm1q_ready || !s && io.vec_iface.vximm1q_user_ready
val mask_ximm2q_ready = !vec_dec.io.sigs.enq_ximm2q || s && io.vec_iface.vximm2q_ready || !s && io.vec_iface.vximm2q_user_ready
val mask_cntq_ready = !vec_dec.io.sigs.enq_cntq || io.vec_iface.vcntq_ready
val mask_pfcmdq_ready = !vec_dec.io.sigs.enq_pfcmdq || io.vec_iface.vpfcmdq_ready
val mask_pfximm1q_ready = !vec_dec.io.sigs.enq_pfximm1q || io.vec_iface.vpfximm1q_ready
val mask_pfximm2q_ready = !vec_dec.io.sigs.enq_pfximm2q || io.vec_iface.vpfximm2q_ready
val mask_pfcntq_ready = !vec_dec.io.sigs.enq_pfcntq || io.vec_iface.vpfcntq_ready
vec_stalld =
vec_dec.io.sigs.valid && (
!mask_cmdq_ready || !mask_ximm1q_ready || !mask_ximm2q_ready || !mask_cntq_ready ||
!mask_pfcmdq_ready || !mask_pfximm1q_ready || !mask_pfximm2q_ready || !mask_pfcntq_ready) ||
id_vec_val && id_vfence && !vec.io.vfence_ready
vec_replay = vec.io.replay vec_replay = vec.io.replay
vec_stalld = vec.io.stalld || id_vfence_cv && !vec.io.vfence_ready
vec_irq = vec.io.irq vec_irq = vec.io.irq
vec_irq_cause = vec.io.irq_cause vec_irq_cause = vec.io.irq_cause
} }
@ -802,7 +819,6 @@ class rocketCtrl extends Component
id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr || id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr ||
id_stall_fpu || id_stall_fpu ||
id_mem_val.toBool && !(io.dmem.req_rdy && io.dtlb_rdy) || id_mem_val.toBool && !(io.dmem.req_rdy && io.dtlb_rdy) ||
id_vec_val.toBool && !(io.vec_iface.vcmdq_ready && io.vec_iface.vximm1q_ready && io.vec_iface.vximm2q_ready) || // being conservative
((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy || ((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy ||
vec_stalld vec_stalld
); );

274
rocket/src/main/scala/ctrl_vec.scala
View File

@ -46,8 +46,6 @@ class ioCtrlVecInterface extends Bundle
val irq_cause = UFix(5, INPUT) val irq_cause = UFix(5, INPUT)
val exception = Bool(OUTPUT) val exception = Bool(OUTPUT)
val exception_ack_valid = Bool(INPUT)
val exception_ack_ready = Bool(OUTPUT)
val evac = Bool(OUTPUT) val evac = Bool(OUTPUT)
val kill = Bool(OUTPUT) val kill = Bool(OUTPUT)
@ -64,18 +62,45 @@ class ioCtrlVec extends Bundle
val exception = Bool(INPUT) val exception = Bool(INPUT)
val eret = Bool(INPUT) val eret = Bool(INPUT)
val replay = Bool(OUTPUT) val replay = Bool(OUTPUT)
val stalld = Bool(OUTPUT)
val vfence_ready = Bool(OUTPUT) val vfence_ready = Bool(OUTPUT)
val irq = Bool(OUTPUT) val irq = Bool(OUTPUT)
val irq_cause = UFix(5, OUTPUT) val irq_cause = UFix(5, OUTPUT)
} }
class rocketCtrlVec extends Component class rocketCtrlVecSigs extends Bundle
{ {
val io = new ioCtrlVec() val valid = Bool()
val sel_vcmd = Bits(width = 3)
val sel_vimm = Bits(width = 1)
val sel_vimm2 = Bits(width = 1)
val wen = Bool()
val fn = Bits(width = 2)
val appvlmask = Bool()
val enq_cmdq = Bool()
val enq_ximm1q = Bool()
val enq_ximm2q = Bool()
val enq_cntq = Bool()
val enq_pfcmdq = Bool()
val enq_pfximm1q = Bool()
val enq_pfximm2q = Bool()
val enq_pfcntq = Bool()
val pfaq = Bool()
val vfence = Bool()
val xcptevac = Bool()
val xcptkill = Bool()
val xcpthold = Bool()
}
class rocketCtrlVecDecoder extends Component
{
val io = new Bundle
{
val inst = Bits(32, INPUT)
val sigs = new rocketCtrlVecSigs().asOutput
}
val veccs = val veccs =
ListLookup(io.dpath.inst, ListLookup(io.inst,
// appvlmask // appvlmask
// | vcmdq // | vcmdq
// | | vximm1q // | | vximm1q
@ -85,158 +110,175 @@ class rocketCtrlVec extends Component
// | | | | | | vpfximm1q // | | | | | | vpfximm1q
// | | | | | | | vpfximm2q // | | | | | | | vpfximm2q
// | | | | | | | | vpfcntq // | | | | | | | | vpfcntq
// wen | | | | | | | | | pfq // | | | | | | | | | pfq
// val vcmd vimm vimm2 | fn | | | | | | | | | | fence_cv // | | | | | | | | | | vfence
// | | | | | | | | | | | | | | | | | xcptwait // | | | | | | | | | | | xcptevac
// | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | xcptkill
List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,N,N,N,N),Array( // wen | | | | | | | | | | | | | xcpthold
VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), // val vcmd vimm vimm2 | fn | | | | | | | | | | | | | |
VVCFG-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, N,VEC_CFG, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), // | | | | | | | | | | | | | | | | | | | |
VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,N,N,N),Array(
VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N,N), VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N,N), VVCFG-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, N,VEC_CFG, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N,N), VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N,N), VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N),
FENCE_V_L-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N,N), VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N),
FENCE_V_G-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N,N), VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N),
VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N),
VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), FENCE_V_L-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N),
VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), FENCE_V_G-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N),
VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,Y,N,N,N,Y,N,N,N,N,N), VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_FN_N, N,N,Y,N,N,N,Y,N,N,Y,N,N,N,N,N), VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_ALU,N,VEC_FN_N, N,N,N,Y,N,N,N,Y,N,Y,N,N,N,N,N), VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,Y,N,N,N,Y,Y,N,N,N,N,N), VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,Y,N,N,N,Y,N,N,N,N),
VXCPTEVAC-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,Y,N,N,N), VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_FN_N, N,N,Y,N,N,N,Y,N,N,Y,N,N,N,N),
VXCPTKILL-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,Y,N,N), VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_ALU,N,VEC_FN_N, N,N,N,Y,N,N,N,Y,N,Y,N,N,N,N),
VXCPTWAIT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,Y,N), VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,Y,N,N,N,Y,Y,N,N,N,N),
VXCPTHOLD-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,N,Y) VXCPTEVAC-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,Y,N,N),
VXCPTKILL-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,Y,N),
VXCPTHOLD-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,Y)
)) ))
val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_sel_vimm2 :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs val valid :: sel_vcmd :: sel_vimm :: sel_vimm2 :: wen :: fn :: appvlmask :: veccs0 = veccs
val wb_vec_cmdq_enq :: wb_vec_ximm1q_enq :: wb_vec_ximm2q_enq :: wb_vec_cntq_enq :: veccs1 = veccs0 val enq_cmdq :: enq_ximm1q :: enq_ximm2q :: enq_cntq :: veccs1 = veccs0
val wb_vec_pfcmdq_enq :: wb_vec_pfximm1q_enq :: wb_vec_pfximm2q_enq :: wb_vec_pfcntq_enq :: veccs2 = veccs1 val enq_pfcmdq :: enq_pfximm1q :: enq_pfximm2q :: enq_pfcntq :: veccs2 = veccs1
val wb_vec_pfaq :: wb_vec_fence_cv :: wb_vec_xcptevac :: wb_vec_xcptkill :: wb_vec_xcptwait :: wb_vec_xcpthold :: Nil = veccs2 val pfaq :: vfence :: xcptevac :: xcptkill :: xcpthold :: Nil = veccs2
val valid_common = io.valid && io.sr_ev && wb_vec_val && !(wb_vec_appvlmask && io.dpath.appvl0) io.sigs.valid := valid.toBool
io.sigs.sel_vcmd := sel_vcmd
io.sigs.sel_vimm := sel_vimm
io.sigs.sel_vimm2 := sel_vimm2
io.sigs.wen := wen.toBool
io.sigs.fn := fn
io.sigs.appvlmask := appvlmask.toBool
io.sigs.enq_cmdq := enq_cmdq.toBool
io.sigs.enq_ximm1q := enq_ximm1q.toBool
io.sigs.enq_ximm2q := enq_ximm2q.toBool
io.sigs.enq_cntq := enq_cntq.toBool
io.sigs.enq_pfcmdq := enq_pfcmdq.toBool
io.sigs.enq_pfximm1q := enq_pfximm1q.toBool
io.sigs.enq_pfximm2q := enq_pfximm2q.toBool
io.sigs.enq_pfcntq := enq_pfcntq.toBool
io.sigs.pfaq := pfaq.toBool
io.sigs.vfence := vfence.toBool
io.sigs.xcptevac := xcptevac.toBool
io.sigs.xcptkill := xcptkill.toBool
io.sigs.xcpthold := xcpthold.toBool
}
val wb_vec_pfcmdq_enq_mask_pfq = wb_vec_pfcmdq_enq && (!wb_vec_pfaq || io.dpath.pfq) class rocketCtrlVec extends Component
val wb_vec_pfximm1q_enq_mask_pfq = wb_vec_pfximm1q_enq && (!wb_vec_pfaq || io.dpath.pfq) {
val wb_vec_pfximm2q_enq_mask_pfq = wb_vec_pfximm2q_enq && (!wb_vec_pfaq || io.dpath.pfq) val io = new ioCtrlVec()
val wb_vec_pfcntq_enq_mask_pfq = wb_vec_pfcntq_enq && (!wb_vec_pfaq || io.dpath.pfq)
val mask_wb_vec_cmdq_ready = !wb_vec_cmdq_enq || io.s && io.iface.vcmdq_ready || !io.s && io.iface.vcmdq_user_ready val dec = new rocketCtrlVecDecoder()
val mask_wb_vec_ximm1q_ready = !wb_vec_ximm1q_enq || io.s && io.iface.vximm1q_ready || !io.s && io.iface.vximm1q_user_ready dec.io.inst := io.dpath.inst
val mask_wb_vec_ximm2q_ready = !wb_vec_ximm2q_enq || io.s && io.iface.vximm2q_ready || !io.s && io.iface.vximm2q_user_ready
val mask_wb_vec_cntq_ready = !wb_vec_cntq_enq || io.iface.vcntq_ready
val mask_wb_vec_pfcmdq_ready = !wb_vec_pfcmdq_enq_mask_pfq || io.iface.vpfcmdq_ready
val mask_wb_vec_pfximm1q_ready = !wb_vec_pfximm1q_enq_mask_pfq || io.iface.vpfximm1q_ready
val mask_wb_vec_pfximm2q_ready = !wb_vec_pfximm2q_enq_mask_pfq || io.iface.vpfximm2q_ready
val mask_wb_vec_pfcntq_ready = !wb_vec_pfcntq_enq_mask_pfq || io.iface.vpfcntq_ready
io.dpath.wen := wb_vec_wen.toBool val valid_common = io.valid && io.sr_ev && dec.io.sigs.valid && !(dec.io.sigs.appvlmask && io.dpath.appvl0)
io.dpath.fn := wb_vec_fn
io.dpath.sel_vcmd := wb_sel_vcmd val enq_pfcmdq_mask_pfq = dec.io.sigs.enq_pfcmdq && (!dec.io.sigs.pfaq || io.dpath.pfq)
io.dpath.sel_vimm := wb_sel_vimm val enq_pfximm1q_mask_pfq = dec.io.sigs.enq_pfximm1q && (!dec.io.sigs.pfaq || io.dpath.pfq)
io.dpath.sel_vimm2 := wb_sel_vimm2 val enq_pfximm2q_mask_pfq = dec.io.sigs.enq_pfximm2q && (!dec.io.sigs.pfaq || io.dpath.pfq)
val enq_pfcntq_mask_pfq = dec.io.sigs.enq_pfcntq && (!dec.io.sigs.pfaq || io.dpath.pfq)
val mask_cmdq_ready = !dec.io.sigs.enq_cmdq || io.s && io.iface.vcmdq_ready || !io.s && io.iface.vcmdq_user_ready
val mask_ximm1q_ready = !dec.io.sigs.enq_ximm1q || io.s && io.iface.vximm1q_ready || !io.s && io.iface.vximm1q_user_ready
val mask_ximm2q_ready = !dec.io.sigs.enq_ximm2q || io.s && io.iface.vximm2q_ready || !io.s && io.iface.vximm2q_user_ready
val mask_cntq_ready = !dec.io.sigs.enq_cntq || io.iface.vcntq_ready
val mask_pfcmdq_ready = !enq_pfcmdq_mask_pfq || io.iface.vpfcmdq_ready
val mask_pfximm1q_ready = !enq_pfximm1q_mask_pfq || io.iface.vpfximm1q_ready
val mask_pfximm2q_ready = !enq_pfximm2q_mask_pfq || io.iface.vpfximm2q_ready
val mask_pfcntq_ready = !enq_pfcntq_mask_pfq || io.iface.vpfcntq_ready
io.dpath.wen := dec.io.sigs.wen
io.dpath.fn := dec.io.sigs.fn
io.dpath.sel_vcmd := dec.io.sigs.sel_vcmd
io.dpath.sel_vimm := dec.io.sigs.sel_vimm
io.dpath.sel_vimm2 := dec.io.sigs.sel_vimm2
io.iface.vcmdq_valid := io.iface.vcmdq_valid :=
valid_common && valid_common &&
wb_vec_cmdq_enq && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && dec.io.sigs.enq_cmdq && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vximm1q_valid := io.iface.vximm1q_valid :=
valid_common && valid_common &&
mask_wb_vec_cmdq_ready && wb_vec_ximm1q_enq && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && mask_cmdq_ready && dec.io.sigs.enq_ximm1q && mask_ximm2q_ready && mask_cntq_ready &&
mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vximm2q_valid := io.iface.vximm2q_valid :=
valid_common && valid_common &&
mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && wb_vec_ximm2q_enq && mask_wb_vec_cntq_ready && mask_cmdq_ready && mask_ximm1q_ready && dec.io.sigs.enq_ximm2q && mask_cntq_ready &&
mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vcntq_valid := io.iface.vcntq_valid :=
valid_common && valid_common &&
mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && wb_vec_cntq_enq && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && dec.io.sigs.enq_cntq &&
mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vpfcmdq_valid := io.iface.vpfcmdq_valid :=
valid_common && valid_common &&
mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
wb_vec_pfcmdq_enq_mask_pfq && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready enq_pfcmdq_mask_pfq && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vpfximm1q_valid := io.iface.vpfximm1q_valid :=
valid_common && valid_common &&
mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
mask_wb_vec_pfcmdq_ready && wb_vec_pfximm1q_enq_mask_pfq && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready mask_pfcmdq_ready && enq_pfximm1q_mask_pfq && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vpfximm2q_valid := io.iface.vpfximm2q_valid :=
valid_common && valid_common &&
mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && wb_vec_pfximm2q_enq_mask_pfq && mask_wb_vec_pfcntq_ready mask_pfcmdq_ready && mask_pfximm1q_ready && enq_pfximm2q_mask_pfq && mask_pfcntq_ready
io.iface.vpfcntq_valid := io.iface.vpfcntq_valid :=
valid_common && valid_common &&
mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && wb_vec_pfcntq_enq_mask_pfq mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && enq_pfcntq_mask_pfq
io.replay := valid_common && ( io.replay := valid_common && (
wb_vec_cmdq_enq && !io.iface.vcmdq_ready || !mask_cmdq_ready || !mask_ximm1q_ready || !mask_ximm2q_ready || !mask_cntq_ready ||
wb_vec_ximm1q_enq && !io.iface.vximm1q_ready || !mask_pfcmdq_ready || !mask_pfximm1q_ready || !mask_pfximm2q_ready || !mask_pfcntq_ready ||
wb_vec_ximm2q_enq && !io.iface.vximm2q_ready || dec.io.sigs.vfence && !io.iface.vfence_ready
wb_vec_cntq_enq && !io.iface.vcntq_ready ||
wb_vec_pfcmdq_enq_mask_pfq && !io.iface.vpfcmdq_ready ||
wb_vec_pfximm1q_enq_mask_pfq && !io.iface.vpfximm1q_ready ||
wb_vec_pfximm2q_enq_mask_pfq && !io.iface.vpfximm2q_ready ||
wb_vec_pfcntq_enq_mask_pfq && !io.iface.vpfcntq_ready ||
wb_vec_fence_cv && !io.iface.vfence_ready
) )
val reg_xcptwait = Reg(resetVal = Bool(false))
val do_xcptwait = valid_common && wb_vec_xcptwait && !io.replay
when (io.iface.exception_ack_valid) { reg_xcptwait := Bool(false) }
when (do_xcptwait) { reg_xcptwait := Bool(true) }
io.iface.exception := io.exception && io.sr_ev io.iface.exception := io.exception && io.sr_ev
io.iface.exception_ack_ready := reg_xcptwait
val reg_hold = Reg(resetVal = Bool(false)) val reg_hold = Reg(resetVal = Bool(false))
when (valid_common && wb_vec_xcpthold) { reg_hold := Bool(true) } when (valid_common && dec.io.sigs.xcpthold) { reg_hold := Bool(true) }
when (io.eret) { reg_hold := Bool(false) } when (io.eret) { reg_hold := Bool(false) }
io.iface.evac := valid_common && wb_vec_xcptevac.toBool io.iface.evac := valid_common && dec.io.sigs.xcptevac
io.iface.kill := valid_common && wb_vec_xcptkill.toBool io.iface.kill := valid_common && dec.io.sigs.xcptkill
io.iface.hold := reg_hold io.iface.hold := reg_hold
io.stalld := reg_xcptwait
io.vfence_ready := !io.sr_ev || io.iface.vfence_ready io.vfence_ready := !io.sr_ev || io.iface.vfence_ready
io.irq := io.iface.irq io.irq := io.iface.irq
io.irq_cause := io.iface.irq_cause io.irq_cause := io.iface.irq_cause

2
rocket/src/main/scala/dpath.scala
View File

@ -387,7 +387,7 @@ class rocketDpath extends Component
vec.io.ctrl <> io.vec_ctrl vec.io.ctrl <> io.vec_ctrl
io.vec_iface <> vec.io.iface io.vec_iface <> vec.io.iface
vec.io.valid := io.ctrl.wb_valid vec.io.valid := io.ctrl.wb_valid && pcr.io.status(SR_EV)
vec.io.inst := wb_reg_inst vec.io.inst := wb_reg_inst
vec.io.waddr := wb_reg_vec_waddr vec.io.waddr := wb_reg_vec_waddr
vec.io.raddr1 := wb_reg_raddr1 vec.io.raddr1 := wb_reg_raddr1

1
rocket/src/main/scala/instructions.scala
View File

@ -253,7 +253,6 @@ object Instructions
val VENQCNT = Bits("b00000_?????_?????_1100000110_1111011",32) val VENQCNT = Bits("b00000_?????_?????_1100000110_1111011",32)
val VXCPTEVAC = Bits("b00000_?????_00000_1100000000_1111011",32) val VXCPTEVAC = Bits("b00000_?????_00000_1100000000_1111011",32)
val VXCPTKILL = Bits("b00000_00000_00000_1000000010_1111011",32) val VXCPTKILL = Bits("b00000_00000_00000_1000000010_1111011",32)
val VXCPTWAIT = Bits("b00000_00000_00000_1100000001_1111011",32)
val VXCPTHOLD = Bits("b00000_00000_00000_1100000010_1111011",32) val VXCPTHOLD = Bits("b00000_00000_00000_1100000010_1111011",32)
val NOP = ADDI & Bits("b00000000000000000000001111111111", 32); val NOP = ADDI & Bits("b00000000000000000000001111111111", 32);