256 lines
9.8 KiB
Scala
256 lines
9.8 KiB
Scala
package rocket
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import Chisel._;
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import Node._;
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import Constants._;
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import hwacha._
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class ioDebug(view: List[String] = null) extends Bundle(view)
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{
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val error_mode = Bool(OUTPUT);
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}
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class ioRocket extends Bundle()
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{
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val debug = new ioDebug();
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val host = new ioHTIF();
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val imem = new ioImem().flip
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val vimem = new ioImem().flip
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val dmem = new ioDmem().flip
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}
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class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
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{
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val io = new ioRocket();
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val ctrl = new rocketCtrl();
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val dpath = new rocketDpath();
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val dtlb = new rocketDTLB(DTLB_ENTRIES);
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val itlb = new rocketITLB(ITLB_ENTRIES);
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val vitlb = new rocketITLB(VITLB_ENTRIES)
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val ptw = new rocketPTW();
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val arb = new rocketDmemArbiter(DCACHE_PORTS)
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var vu: vu = null
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if (HAVE_VEC)
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{
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vu = new vu()
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// cpu, vector prefetch, and vector use the DTLB
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val dtlbarb = new RRArbiter(3)({new ioDTLB_CPU_req_bundle()})
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val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3)))
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when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
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// tlb respones come out a cycle later
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val chosen_vec = dtlbchosen === Bits(DTLB_VEC)
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val chosen_pf = dtlbchosen === Bits(DTLB_VPF)
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val chosen_cpu = dtlbchosen === Bits(DTLB_CPU)
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dtlbarb.io.in(DTLB_VEC) <> vu.io.vec_tlb_req
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vu.io.vec_tlb_resp.xcpt_ld := chosen_vec && dtlb.io.cpu_resp.xcpt_ld
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vu.io.vec_tlb_resp.xcpt_st := chosen_vec && dtlb.io.cpu_resp.xcpt_st
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vu.io.vec_tlb_resp.xcpt_pf := Bool(false)
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vu.io.vec_tlb_resp.miss := chosen_vec && dtlb.io.cpu_resp.miss
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vu.io.vec_tlb_resp.ppn := dtlb.io.cpu_resp.ppn
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dtlbarb.io.in(DTLB_VPF) <> vu.io.vec_pftlb_req
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vu.io.vec_pftlb_resp.xcpt_ld := Bool(false)
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vu.io.vec_pftlb_resp.xcpt_st := Bool(false)
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vu.io.vec_pftlb_resp.xcpt_pf := chosen_pf && dtlb.io.cpu_resp.xcpt_pf
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vu.io.vec_pftlb_resp.miss := chosen_pf && dtlb.io.cpu_resp.miss
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vu.io.vec_pftlb_resp.ppn := dtlb.io.cpu_resp.ppn
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// connect DTLB to ctrl+dpath
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dtlbarb.io.in(DTLB_CPU).valid := ctrl.io.dtlb_val
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dtlbarb.io.in(DTLB_CPU).bits.kill := ctrl.io.dtlb_kill
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dtlbarb.io.in(DTLB_CPU).bits.cmd := ctrl.io.dmem.req_cmd
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dtlbarb.io.in(DTLB_CPU).bits.asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
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dtlbarb.io.in(DTLB_CPU).bits.vpn := dpath.io.dtlb.vpn
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ctrl.io.dtlb_rdy := dtlbarb.io.in(DTLB_CPU).ready
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ctrl.io.xcpt_dtlb_ld := chosen_cpu && dtlb.io.cpu_resp.xcpt_ld
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ctrl.io.xcpt_dtlb_st := chosen_cpu && dtlb.io.cpu_resp.xcpt_st
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ctrl.io.dtlb_miss := chosen_cpu && dtlb.io.cpu_resp.miss
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dtlb.io.cpu_req <> dtlbarb.io.out
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}
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else
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{
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// connect DTLB to ctrl+dpath
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dtlb.io.cpu_req.valid := ctrl.io.dtlb_val
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dtlb.io.cpu_req.bits.kill := ctrl.io.dtlb_kill
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dtlb.io.cpu_req.bits.cmd := ctrl.io.dmem.req_cmd
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dtlb.io.cpu_req.bits.asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
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dtlb.io.cpu_req.bits.vpn := dpath.io.dtlb.vpn
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ctrl.io.xcpt_dtlb_ld := dtlb.io.cpu_resp.xcpt_ld
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ctrl.io.xcpt_dtlb_st := dtlb.io.cpu_resp.xcpt_st
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ctrl.io.dtlb_rdy := dtlb.io.cpu_req.ready
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ctrl.io.dtlb_miss := dtlb.io.cpu_resp.miss
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}
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dtlb.io.invalidate := dpath.io.ptbr_wen
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dtlb.io.status := dpath.io.ctrl.status
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arb.io.requestor(DMEM_CPU).req_ppn := dtlb.io.cpu_resp.ppn
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ctrl.io.dmem.req_rdy := dtlb.io.cpu_req.ready && arb.io.requestor(DMEM_CPU).req_rdy
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// connect page table walker to TLBs, page table base register (from PCR)
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// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
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ptw.io.dtlb <> dtlb.io.ptw;
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ptw.io.itlb <> itlb.io.ptw;
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ptw.io.vitlb <> vitlb.io.ptw
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ptw.io.ptbr := dpath.io.ptbr;
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arb.io.requestor(DMEM_PTW) <> ptw.io.dmem
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arb.io.dmem <> io.dmem
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ctrl.io.dpath <> dpath.io.ctrl;
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dpath.io.host <> io.host;
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dpath.io.debug <> io.debug;
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// FIXME: try to make this more compact
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// connect ITLB to I$, ctrl, dpath
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itlb.io.cpu.invalidate := dpath.io.ptbr_wen;
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itlb.io.cpu.status := dpath.io.ctrl.status;
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itlb.io.cpu.req_val := ctrl.io.imem.req_val;
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itlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
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itlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS,PGIDX_BITS);
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io.imem.req_idx := dpath.io.imem.req_addr(PGIDX_BITS-1,0);
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io.imem.req_ppn := itlb.io.cpu.resp_ppn;
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io.imem.req_val := ctrl.io.imem.req_val;
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io.imem.invalidate := ctrl.io.dpath.flush_inst;
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ctrl.io.imem.resp_val := io.imem.resp_val;
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dpath.io.imem.resp_data := io.imem.resp_data;
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ctrl.io.xcpt_itlb := itlb.io.cpu.exception;
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io.imem.itlb_miss := itlb.io.cpu.resp_miss;
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// connect arbiter to ctrl+dpath+DTLB
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arb.io.requestor(DMEM_CPU) <> ctrl.io.dmem
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arb.io.requestor(DMEM_CPU) <> dpath.io.dmem
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var fpu: rocketFPU = null
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if (HAVE_FPU)
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{
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fpu = new rocketFPU(4,6)
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dpath.io.fpu <> fpu.io.dpath
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ctrl.io.fpu <> fpu.io.ctrl
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}
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else
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{
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ctrl.io.fpu.dec.valid := Bool(false)
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ctrl.io.fpu.dec.wen := Bool(false)
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}
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if (HAVE_VEC)
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{
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dpath.io.vec_ctrl <> ctrl.io.vec_dpath
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// hooking up vector I$
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vitlb.io.cpu.invalidate := dpath.io.ptbr_wen
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vitlb.io.cpu.status := dpath.io.ctrl.status
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vitlb.io.cpu.req_val := vu.io.imem_req.valid
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vitlb.io.cpu.req_asid := Bits(0,ASID_BITS) // FIXME: connect to PCR
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vitlb.io.cpu.req_vpn := vu.io.imem_req.bits(VADDR_BITS,PGIDX_BITS).toUFix
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io.vimem.req_idx := vu.io.imem_req.bits(PGIDX_BITS-1,0)
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io.vimem.req_ppn := vitlb.io.cpu.resp_ppn
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io.vimem.req_val := vu.io.imem_req.valid
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io.vimem.invalidate := ctrl.io.dpath.flush_inst
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vu.io.imem_req.ready := Bool(true)
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vu.io.imem_resp.valid := io.vimem.resp_val
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vu.io.imem_resp.bits := io.vimem.resp_data
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vu.io.vitlb_exception := vitlb.io.cpu.exception
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io.vimem.itlb_miss := vitlb.io.cpu.resp_miss
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// hooking up vector command queues
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vu.io.vec_cmdq.valid := ctrl.io.vec_iface.vcmdq_valid
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vu.io.vec_cmdq.bits := dpath.io.vec_iface.vcmdq_bits
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vu.io.vec_ximm1q.valid := ctrl.io.vec_iface.vximm1q_valid
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vu.io.vec_ximm1q.bits := dpath.io.vec_iface.vximm1q_bits
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vu.io.vec_ximm2q.valid := ctrl.io.vec_iface.vximm2q_valid
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vu.io.vec_ximm2q.bits := dpath.io.vec_iface.vximm2q_bits
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vu.io.vec_cntq.valid := ctrl.io.vec_iface.vcntq_valid
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vu.io.vec_cntq.bits := Cat(dpath.io.vec_iface.vcntq_last, dpath.io.vec_iface.vcntq_bits)
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// prefetch queues
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vu.io.vec_pfcmdq.valid := ctrl.io.vec_iface.vpfcmdq_valid
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vu.io.vec_pfcmdq.bits := dpath.io.vec_iface.vcmdq_bits
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vu.io.vec_pfximm1q.valid := ctrl.io.vec_iface.vpfximm1q_valid
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vu.io.vec_pfximm1q.bits := dpath.io.vec_iface.vximm1q_bits
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vu.io.vec_pfximm2q.valid := ctrl.io.vec_iface.vpfximm2q_valid
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vu.io.vec_pfximm2q.bits := dpath.io.vec_iface.vximm2q_bits
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vu.io.vec_pfcntq.valid := ctrl.io.vec_iface.vpfcntq_valid
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vu.io.vec_pfcntq.bits := dpath.io.vec_iface.vcntq_bits
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// don't have to use pf ready signals
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// if cmdq is not a load or store
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ctrl.io.vec_iface.vcmdq_ready := vu.io.vec_cmdq.ready
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ctrl.io.vec_iface.vximm1q_ready := vu.io.vec_ximm1q.ready
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ctrl.io.vec_iface.vximm2q_ready := vu.io.vec_ximm2q.ready
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ctrl.io.vec_iface.vcntq_ready := vu.io.vec_cntq.ready
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ctrl.io.vec_iface.vpfcmdq_ready := vu.io.vec_pfcmdq.ready
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ctrl.io.vec_iface.vpfximm1q_ready := vu.io.vec_pfximm1q.ready
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ctrl.io.vec_iface.vpfximm2q_ready := vu.io.vec_pfximm2q.ready
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ctrl.io.vec_iface.vpfcntq_ready := vu.io.vec_pfcntq.ready
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// user level vector command queue ready signals
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ctrl.io.vec_iface.vcmdq_user_ready := vu.io.vec_cmdq_user_ready
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ctrl.io.vec_iface.vximm1q_user_ready := vu.io.vec_ximm1q_user_ready
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ctrl.io.vec_iface.vximm2q_user_ready := vu.io.vec_ximm2q_user_ready
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// fences
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ctrl.io.vec_iface.vfence_ready := vu.io.vec_fence_ready
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// irqs
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ctrl.io.vec_iface.irq := vu.io.irq
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ctrl.io.vec_iface.irq_cause := vu.io.irq_cause
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dpath.io.vec_iface.irq_aux := vu.io.irq_aux
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// exceptions
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vu.io.xcpt.exception := ctrl.io.vec_iface.exception
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vu.io.xcpt.evac := ctrl.io.vec_iface.evac
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vu.io.xcpt.evac_addr := dpath.io.vec_iface.evac_addr.toUFix
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vu.io.xcpt.kill := ctrl.io.vec_iface.kill
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vu.io.xcpt.hold := ctrl.io.vec_iface.hold
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// hooking up vector memory interface
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val storegen = new StoreDataGen
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storegen.io.typ := vu.io.dmem_req.bits.typ
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storegen.io.din := vu.io.dmem_req.bits.data
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arb.io.requestor(DMEM_VU).req_val := vu.io.dmem_req.valid
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arb.io.requestor(DMEM_VU).req_kill := vu.io.dmem_req.bits.kill
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arb.io.requestor(DMEM_VU).req_cmd := vu.io.dmem_req.bits.cmd
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arb.io.requestor(DMEM_VU).req_type := vu.io.dmem_req.bits.typ
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arb.io.requestor(DMEM_VU).req_idx := vu.io.dmem_req.bits.idx
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arb.io.requestor(DMEM_VU).req_ppn := Reg(vu.io.dmem_req.bits.ppn)
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arb.io.requestor(DMEM_VU).req_data := Reg(storegen.io.dout)
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arb.io.requestor(DMEM_VU).req_tag := vu.io.dmem_req.bits.tag
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vu.io.dmem_req.ready := arb.io.requestor(DMEM_VU).req_rdy
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vu.io.dmem_resp.valid := Reg(arb.io.requestor(DMEM_VU).resp_val)
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vu.io.dmem_resp.bits.nack := arb.io.requestor(DMEM_VU).resp_nack
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vu.io.dmem_resp.bits.data := arb.io.requestor(DMEM_VU).resp_data_subword
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vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(DMEM_VU).resp_tag)
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vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(DMEM_VU).resp_type)
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// share vector integer multiplier with rocket
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dpath.io.vec_imul_req <> vu.io.cp_imul_req
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dpath.io.vec_imul_resp <> vu.io.cp_imul_resp
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// share sfma and dfma pipelines with rocket
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fpu.io.sfma <> vu.io.cp_sfma
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fpu.io.dfma <> vu.io.cp_dfma
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}
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else
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{
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arb.io.requestor(DMEM_VU).req_val := Bool(false)
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if (HAVE_FPU)
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{
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fpu.io.sfma.valid := Bool(false)
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fpu.io.dfma.valid := Bool(false)
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}
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}
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}
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