riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Implement misa.C proposal

Browse Source 
This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.
This commit is contained in:
Andrew Waterman 2018-02-22 15:12:19 -08:00
parent c1ee31d133
commit aad75f2285
2 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/CSR.scala
View File

@ -837,6 +837,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) }
}
}
def formEPC(x: UInt) = ~(~x | Cat(!reg_misa('c'-'a'), UInt(1)))
def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U))
def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)
}

2
src/main/scala/rocket/RocketCore.scala
View File

@ -228,12 +228,14 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
bpu.io.pc := ibuf.io.pc
bpu.io.ea := mem_reg_wdata
val id_pc_misaligned = !csr.io.status.isa('c'-'a') && ibuf.io.pc(1)
val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0
val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1
val (id_xcpt, id_cause) = checkExceptions(List(
(csr.io.interrupt, csr.io.interrupt_cause),
(bpu.io.debug_if, UInt(CSR.debugTriggerCause)),
(bpu.io.xcpt_if, UInt(Causes.breakpoint)),
(id_pc_misaligned, UInt(Causes.misaligned_fetch)),
(id_xcpt0.pf.inst, UInt(Causes.fetch_page_fault)),
(id_xcpt0.ae.inst, UInt(Causes.fetch_access)),
(id_xcpt1.pf.inst, UInt(Causes.fetch_page_fault)),